PCA9511ADR2G Просмотр технического описания (PDF) - ON Semiconductor

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производитель

PCA9511ADR2G

Hot Swappable I2C-Bus and SMBus Bus Buffer

ON Semiconductor 

PCA9511A

CHARACTERISTICS VCC = 2.7 V to 5.5 V, unless otherwise specified.

Symbol

Parameter

Conditions

TA = −405C to +855C

Min

Typ

Max Unit

SUPPLIES

ICC (Note 6)

ICC(sd)

Supply Current

Shutdown Mode Supply Current

START−UP CIRCUITRY

Vpch (Note 6)

Precharge Voltage

VIH(ENABLE)

High−Level Input Voltage

VIL(ENABLE)

II(ENABLE)

ten (Note 7)

tidle(READY)

(Note 6)

tdis(EN−RDY)

tstp(READY)

(Note 8)

tREADY (Note 8)

ILZ(READY)

CI(ENABLE)

(Note 9)

CO(READY)

(Note 9)

VOL(READY)

(Note 6)

Low−Level Input Voltage

Input Current on pin ENABLE

Enable Time

Bus Idle Time to READY Active

Disable Time (ENABLE to READY)

SDAIN to READY delay after STOP

SCLOUT/SDAOUT to READY delay

Off−State Leakage Current on pin

READY

Input Capacitance on pin ENABLE

Input Capacitance on pin ENABLE

Low−Level Output Voltage on pin

READY

VCC = 5.5 V;

VSDAIN = VSCLIN = 0 V

VENABLE = 0 V;

All other pins at VCC or GND

SDA, SCL Floating

VENABLE = 0 V to VCC

VENABLE = VCC

VI = VCC or GND

VI = VCC or GND

VENABLE = VCC; Ipu = 3 mA

3.5

6

mA

0.1

mA

0.8

1.1

1.2

V

0.7 x

VCC

V

0.3 x

VCC

V

±0.1

±1

mA

110

ms

50

105

200

ms

30

ns

1.2

ms

0.8

ms

±0.3

mA

1.9

4

pF

2.5

4

pF

0.4

V

RISE TIME ACCELERATORS

Itrt(pu)

(Notes 10, 11)

Transient Boosted Pull−up Current

Positive transition on SDA, SCL;

VCC = 2.7 V;

Slew rate = 1.25 V/ms

1

2

mA

INPUT−OUTPUT CONNECTION

Voffset

(Notes 6, 12, 13)

Offset Voltage

tPLH

Low to High Propagation Delay

10 kW to VCC on SDA, SCL;

VCC = 3.3 V

SCL to SCL and SDA to SDA;

10 kW to VCC; CL = 100 pF

each side

0

110

175

mV

0

ns

SCL to SCL and SDA to SDA;

tPHL

High to Low Propagation Delay

10 kW to VCC; CL = 100 pF

each side

70

ns

ILI

CI(SCL/SDA)

(Note 9)

Input Leakage Current

SCL and SDA Input Capacitance

SDAn, SCLn pins; VCC = 5.5 V

±1

mA

5

7

pF

VOL (Note 6)

Low−Level Output Voltage

VI = 0 V; SDAn, SCLn pins;

Isink = 3 mA, VCC = 2.7 V

0.4

V

6. This specification applies over the full operating temperature range.

7. The enable time can slow considerably for some parts when temperature is < −20°C.

8. Delays that can occur after ENABLE and/or idle times have passed.

9. Guaranteed by design, not production tested.

10. Itrt(pu) varies with temperature and VCC voltage, as shown in the “Typical performance characteristics” section.

11. Input pull−up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage

to the positive supply rail.

12. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function

of the pull−up resistor and VCC voltage is shown in the “Typical performance characteristics” section.

13. Force VSDAIN = VSCLIN = 0.1 V, tie SDAOUT and SCLOUT through 10 kW resistor to VCC and measure the SDAOUT and SCLOUT output.

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