MC33874BPNA/R2 Просмотр технического описания (PDF) - Freescale Semiconductor
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MC33874BPNA/R2 Datasheet PDF : 38 Pages
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI)
Input Logic High-voltage(13)
Input Logic Low-voltage(13)
Input Logic Voltage Hysteresis(14)
VIH
0.7 VDD
–
–
V
VIL
–
–
0.2 VDD
V
VIN(HYS)
100
850
1200
mV
Input Logic Pull-down Current (SCLK, SI, IN[0:3], VIN>0.2 x VDD)
IDWN
5.0
–
20
μA
RST Input Voltage Range
SO, FS Tri-State Capacitance(14)
VRST
CSO
4.5
5.0
5.5
V
–
–
20
pF
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance(15)
Wake Input Clamp Voltage(16)
RDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
VCL(WAKE)
V
ICL(WAKE) < 2.5mA
7.0
–
14
Wake Input Forward Voltage
VF(WAKE)
V
ICL(WAKE) = -2.5mA
- 2.0
–
- 0.3
SO High-state Output Voltage
VSOH
V
IOH = 1.0mA
0.8 VDD
–
–
FS, SO Low-state Output Voltage
VSOL
V
IOL = -1.6mA
–
0.2
0.4
SO Tri-state Leakage Current
ISO(LEAK)
μA
CS > 0.7 x VDD, 0 < VSO < VDD
Input Logic Pull-up Current(17)
- 5.0
0
5.0
IUP
μA
CS, VIN < 0.7 x VDD
FSI Input pin External Pull-down Resistance(18)
5.0
–
20
RFS
kΩ
FSI Disabled, HS[0:3] state according to direct inputs state and SPI
INx_SPI bits and A/O_s bit
FSI Enabled, HS[0:3] OFF
FSI Enabled, HS0 ON, HS[1:3] OFF
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
–
0
1.0
6.0
6.5
7.0
15
17
19
40
Infinite
–
Temperature Feedback
TA = 25°C
Temperature Feedback Derating
TFEED
V
3.8
3.9
4.0
DTFEED
-7.2
-7.5
-7.8
mV/°C
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage referenced to VPWR.
14. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
16. The current must be limited by a series resistance when using voltages > 7.0V.
17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
18. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33874
9
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