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ISL85410

Wide VIN 1A Synchronous Buck Regulator

Renesas Electronics 

ISL85410

Measurements fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)

LX 20V/DIV

VOUT 5V/DIV

VOUT 2V/DIV

IL 500mA/DIV

PG 2V/DIV

200µs/DIV

FIGURE 41. NEGATIVE CURRENT LIMIT RECOVERY, PWM

Detailed Description

The ISL85410 combines a synchronous buck PWM controller

with integrated power switches. The buck controller drives

internal high-side and low-side N-channel MOSFETs to deliver

load current up to 1A. The buck regulator can operate from an

unregulated DC source, such as a battery, with a voltage ranging

from +3V to +40V. An internal LDO provides bias to the low

voltage portions of the IC.

Peak current mode control is utilized to simplify feedback loop

compensation and reject input voltage variation. User selectable

internal feedback loop compensation further simplifies design.

The ISL85410 switches at a default 500kHz.

The buck regulator is equipped with an internal current sensing

circuit and the peak current limit threshold is typically set at

1.5A.

Power-On Reset

The ISL85410 automatically initializes upon receipt of the input

power supply and continually monitors the EN pin state. If EN is

held below its logic rising threshold, the IC is held in shutdown

and consumes typically 2µA from the VIN supply. If EN exceeds

its logic rising threshold, the regulator will enable the bias LDO

and begin to monitor the VCC pin voltage. When the VCC pin

voltage clears its rising POR threshold, the controller will initialize

the switching regulator circuits. If VCC never clears the rising POR

threshold, the controller will not allow the switching regulator to

operate. If VCC falls below its falling POR threshold while the

switching regulator is operating, the switching regulator will be

shut down until VCC returns.

Soft-Start

To avoid large in-rush current, VOUT is slowly increased at start-up

to its final regulated value. Soft-start time is determined by the

SS pin connection. If SS is pulled to VCC, an internal 2ms timer is

selected for soft-start. For other soft-start times, simply connect

a capacitor from SS to GND. In this case, a 5.5µA current pulls up

the SS voltage and the FB pin will follow this ramp until it reaches

the 600mV reference level. Soft-start time for this case is

described by Equation 1:

Timems = CnF0.109

(EQ. 1)

PG 2V/DIV

500µs/DIV

FIGURE 42. OVER-TEMPERATURE PROTECTION, PWM

Power-Good

PG is the open-drain output of a window comparator that

continuously monitors the buck regulator output voltage via the

FB pin. PG is actively held low when EN is low and during the

buck regulator soft-start period. After the soft-start period

completes, PG becomes high impedance provided the FB pin is

within the range specified in the “Electrical Specifications” on

page 7. Should FB exit the specified window, PG will be pulled

low until FB returns. Over-temperature faults also force PG low

until the fault condition is cleared by an attempt to soft-start.

There is an internal 5MΩ internal pull-up resistor.

PWM Control Scheme

The ISL85410 employs peak current-mode pulse-width

modulation (PWM) control for fast transient response and

pulse-by-pulse current limiting, as shown in the “Functional Block

Diagram” on page 5. The current loop consists of the current

sensing circuit, slope compensation ramp, PWM comparator,

oscillator and latch. Current sense trans-resistance is typically

500mV/A and slope compensation rate, Se, is typically 450mV/T

where T is the switching cycle period. The control reference for the

current loop comes from the error amplifier’s output (VCOMP).

A PWM cycle begins when a clock pulse sets the PWM latch and the

upper FET is turned on. Current begins to ramp up in the upper FET

and inductor. This current is sensed (VCSA), converted to a voltage

and summed with the slope compensation signal. This combined

signal is compared to VCOMP and when the signal is equal to VCOMP,

the latch is reset. Upon latch reset, the upper FET is turned off and

the lower FET turned on allowing current to ramp down in the

inductor. The lower FET will remain on until the clock initiates

another PWM cycle. Figure 44 shows the typical operating

waveforms during the PWM operation. The dotted lines illustrate the

sum of the current sense and slope compensation signal.

Output voltage is regulated as the error amplifier varies VCOMP

and thus output inductor current. The error amplifier is a

transconductance type and its output (COMP) is terminated with

a series RC network to GND. This termination is internal

(150k/54pF) if the COMP pin is tied to VCC. Additionally, the

transconductance for COMP = VCC is 50µA/V vs 230µA/V for

external RC connection. Its noninverting input is internally

connected to a 600mV reference voltage and its inverting input is

connected to the output voltage via the FB pin and its associated

divider network.

FN8375 Rev 7.00

March 13, 2015

Page 14 of 21

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