ISL8016IRAJZ Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

производитель

ISL8016IRAJZ

6A Low Quiescent Current High Efficiency Synchronous Buck Regulator

Renesas Electronics 

ISL8016

Pin Descriptions

PIN

1, 19, 20

2, 3, 4

5, 6, 7

8

SYMBOL

PGND

PHASE

VIN

PG

9

SYNCOUT

10

SYNCIN

11

12

13

14

15

16, 17

EN

FS

VSET

ISET

SS

COMP, VFB

18

SGND

EPAD

DESCRIPTION

Power ground.

Switching node connection. Connect to one terminal of the inductor.

Input supply voltage. Connect two 22µF ceramic capacitors to power ground.

Power-good is an open-drain output. Use 10k to 100k pull-up resistor connected between VIN and

PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.

This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or

SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.

SYNCOUT is held at 0V in PFM light load to reduce quiescent current.

Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or

ground for PFM mode. Connect to an external function generator for synchronization with the positive

edge trigger. There is an internal 1M pull-down resistor to prevent an undefined logic state if SYNCIN

is floating.

Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the

output capacitor when driven to low. There is an internal 1M pull-down resistor to prevent an

undefined logic state in case of EN pin float.

This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The

frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz

and configured for internal compensation if FS is connected to VIN.

VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for

no margining, and connect to VIN for +10%.

ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND

for 2A, to VIN for 4A, and keep it floating for 6A.

SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor

from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.

The feedback network of the regulator, VFB, is the negative input to the transconductance error

amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used

(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider

connected to VFB. With a properly selected divider, the output voltage can be set to any voltage

between VIN and the 0.6V reference. While internal compensation offers a solution for many typical

applications, an external compensation network may offer improved performance for some designs.

In addition to regulation, VFB is also used to determine the state of PG.

Short VFB to OUTPUT when using one of the available fixed VOUT options.

Signal ground.

The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many

vias as possible under the pad connecting to the system GND plane for optimal thermal performance.

FN7616 Rev 1.00

May 5, 2011

Page 3 of 22

Share Link: