ISL6415 Просмотр технического описания (PDF) - Renesas Electronics

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ISL6415

Triple Output Regulator with Single Synchronous Buck and Dual LDO

Renesas Electronics 

ISL6415

Electrical Specifications Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V, Compensation

Capacitors = 33nF for LDO1 and LDO2. TA = 25°C. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RESET Current Source

0.4

0.54

0.7

A

RESET/RESET Active Timeout Period (Note 5)

POWER GOOD (PG_LDO)

CT = 0.01F

25

-

-

ms

PGOOD Threshold (Rising)

+11

+15

+18

%

PGOOD Threshold (Falling)

-17

-15

-11

%

PGOOD Output Voltage Low

PGOOD Output Leakage Current

PWM OUTPUT OVERVOLTAGE

IOL = 1mA

VOUT = 3.3V

-

-

0.5

V

-

0.01

0.1

A

Overvoltage Threshold

27

30

33

%

NOTES:

3. Specifications at -40°C and +85°C are guaranteed by design/characterization, not production tested.

4. This is the VIN current consumed when the device is active but not switching. Does not include gate drive current.

5. The dropout voltage is defined as VIN - VOUT, when Vout is 50mV below the value of VOUT for VIN = VOUT + 0.5V.

6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01F) the RESET time is 25ms; at 1000nF (0.1F) the

RESET time would be 250ms.

7. Guaranteed by design, not production tested.

FN9145 Rev 0.00

Dec 27, 2004

Page 7 of 13

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