ISL5729 Просмотр технического описания (PDF) - Renesas Electronics

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Компоненты Описание

производитель

ISL5729

Dual 10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter

Renesas Electronics 

ISL5729

Pin Descriptions

PIN NO.

PIN NAME

PIN DESCRIPTION

11, 19, 26

AGND

Analog ground.

13, 24

28

AVDD

CLK

Analog supply (+2.7V to +3.6V).

Clock input.

27

DGND

Connect to digital ground.

10

20

14, 23

DVDD

FSADJ

NC

Digital supply (+2.7V to +3.6V).

Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output

current = 32 x VFSADJ/RSET.

Not internally connected. Recommend no connect.

12, 25

ICOMP, QCOMP Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with

a 0.1F capacitor.

1-4, 29-38,

43-48

ID9-ID0, QD9-QD0 Digital data input ports. Bit 9 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).

15, 22

IOUTA, QOUTA Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.

16, 21

IOUTB, QOUTB

Complementary current outputs of the device. Full scale output current is achieved on the complementary

outputs when all input bits are set to binary 0.

17

REFIO

Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an

external load. Use 0.1F cap to ground when internal reference is enabled.

18

5-8, 39-42

REFLO

NC

Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.

No connect (NC). Not internally connected. No termination required, may be used for device migration to

higher resolution DACs.

9

SLEEP

Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode.

FN6019 Rev 1.00

February 2002

Page 4 of 13

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