EL7551CUZ-T7 Просмотр технического описания (PDF) - Renesas Electronics
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EL7551CUZ-T7 Datasheet PDF : 9 Pages
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EL7551
EL7551
Applications Information
Circuit Description
General
The EL7551 is a fixed frequency, current mode controlled
DC:DC converter with integrated N-channel power MOSFETs
and a high precision reference. The device incorporates all the
active circuitry required to implement a cost effective, user-
programmable 1A synchronous step-down regulator suitable
for use in DSP core power supplies.
Theory of Operation
The EL7551 is composed of 5 major blocks:
1. PWM Controller
2. NMOS Power FETs and Drive Circuitry
3. Bandgap Reference
4. Oscillator
5. Thermal Shut-down
PWM Controller
The EL7551 regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop and
reference, a pulse width modulator whose duty cycle is
controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down
(buck) converter, the feedback loop forces the time-averaged
output of the modulator to equal the desired output voltage.
Unlike pure voltage-mode control systems, current-mode
control utilizes dual feedback loops to provide both output
voltage and inductor current information to the controller. The
voltage loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output voltage is
equal to the time-averaged of the modulator output, the
relatively large LC time constant found in power supply
applications generally results in low bandwidth and poor
transient response. By directly monitoring changes in inductor
current via a series sense resistor the controller's response
time is not entirely limited by the output LC filter and can react
more quickly to changes in line and load conditions. This feed-
forward characteristic also simplifies AC loop compensation
since it adds a zero to the overall loop response. Through
proper selection of the current-feedback to voltage-feedback
ratio the overall loop response will approach a one-pole
system. The resulting system offers several advantages over
traditional voltage control systems, including simpler loop
compensation, pulse by pulse current limiting, rapid response
to line variation and good load step response.
The heart of the controller is an input direct summing
comparator which sum voltage feedback, current feedback,
slope compensation ramp and power tracking signals together.
Slope compensation is required to prevent system instability
that occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop gain
of the overall system. The slope compensation is fixed
internally and optimized for 500mA inductor ripple current. The
power tracking will not contribute any input to the comparator
steady-state operation. Current feedback is measured by the
patented sensing scheme that senses the inductor current
flowing through the high-side switch whenever it is conducting.
At the beginning of each oscillator period the high-side NMOS
switch is turned on. The comparator inputs are gated off for a
minimum period of time of about 150ns (LEB) after the high-
side switch is turned on to allow the system to settle. The
Leading Edge Blanking (LEB) period prevents the detection of
erroneous voltages at the comparator inputs due to switching
noise. If the inductor current exceeds the maximum current
limit (ILMAX) a secondary over-current comparator will
terminate the high-side switch on time. If ILMAX has not been
reached, the feedback voltage FB derived from the regulator
output voltage VOUT is then compared to the internal
feedback reference voltage. The resultant error voltage is
summed with the current feedback and slope compensation
ramp. The high-side switch remains on until all four comparator
inputs have summed to zero, at which time the high-side
switch is turned off and the low-side switch is turned on.
However, the maximum on-duty ratio of the high-side switch is
limited to 95%. In order to eliminate cross-conduction of the
high-side and low-side switches a 15ns break-before-make
delay is incorporated in the switch drive circuitry. The output
enable (EN) input allows the regulator output to be disabled by
an external logic control signal.
Output Voltage Setting
In general:
VOUT
=
0.975
V
1
+
RR-----21-
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain is changed. This is shown in the performance curves. A
100nA pull-up current from FB to VDD forces VOUT to GND in
the event that FB is floating.
NMOS Power FETs and Drive Circuitry
The EL7551 integrates low on-resistance (60m) NMOS FETs
to achieve high efficiency at 1A. In order to use an NMOS
switch for the high-side drive it is necessary to drive the gate
voltage above the source voltage (LX). This is accomplished
by bootstrapping the VHI pin above the LX voltage with an
external capacitor CVHI and internal switch and diode. When
the low-side switch is turned on and the LX voltage is close to
GND potential, capacitor CVHI is charged through internal
switch to VDRV, typically 5V. At the beginning of the next cycle
the high-side switch turns on and the LX pins begin to rise from
GND to VIN potential. As the LX pin rises the positive plate of
capacitor CVHI follows and eventually reaches a value of
VDRV+VIN, typically 10V, for VDRV=VIN=5V. This voltage is
FN7291 Rev 1.00
March 21, 2006
Page 7 of 9
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