DS2740U Просмотр технического описания (PDF) - Maxim Integrated

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Компоненты Описание

производитель

DS2740U

High-Precision Coulomb Counter

Maxim Integrated 

PART

DS2740U

DS2740BU

VIS1 - VIS2

±204.8mVh

ACR RANGE

20mΩ

RSNS

15mΩ

10mΩ

±10.24Ah ±13.65Ah ±20.48Ah

5mΩ

±40.96Ah

DS2740

MEMORY

The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of

a two-byte register is read, both the MSB and LSB are latched and held for the duration of the Read Data

command to prevent updates during the read and ensure synchronization between the two register bytes.

For consistent results, always read the MSB and the LSB of a two-byte register during the same Read

Data command sequence.

Table 3. MEMORY MAP

ADDRESS (HEX)

DESCRIPTION

00

Reserved

01

Status Register

02 to 07

Reserved

08

Special Feature Register

09 to 0D

Reserved

0E

Current Register MSB

0F

Current Register LSB

10

Accumulated Current Register MSB

11

Accumulated Current Register LSB

12 to FF

Reserved

READ/WRITE

—

R/W

—

R/W

—

R

R

R/W

R/W

—

STATUS REGISTER

The format of the status register is shown in Figure 5. The function of each bit is described in detail in the

following paragraphs.

Figure 5. STATUS REGISTER FORMAT

BIT 7

X

BIT 6

SMOD

ADDRESS 01h

BIT 5 BIT 4 BIT 3

X RNAOP X

BIT 2

X

BIT 1

X

BIT 0

X

SMOD—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter Sleep mode when DQ is low for

2s. A value of 0 disables DQ related transitions to Sleep mode. The power-up default of SMOD = 0.

RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address

command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.

X—Reserved bits.

7 of 16

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