DS21Q44 Просмотр технического описания (PDF) - Maxim Integrated
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DS21Q44 Datasheet PDF : 105 Pages
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DS21Q44
TABLE OF CONTENTS
1. INTRODUCTION ..............................................................................................................................2
2. DS21Q44 PIN DESCRIPTION .........................................................................................................7
3. DS21Q44 PIN FUNCTION DESCRIPTION .................................................................................13
4. DS21Q44 REGISTER MAP .............................................................................................................20
5. PARALLEL PORT ...........................................................................................................................24
6. CONTROL, ID, AND TEST REGISTERS.....................................................................................24
7. STATUS AND INFORMATION REGISTERS .............................................................................35
8. ERROR COUNT REGISTERS........................................................................................................41
9. DS0 MONITORING FUNCTION ...................................................................................................44
10. SIGNALING OPERATION ............................................................................................................46
10.1 PROCESSOR-BASED SIGNALING ........................................................................................46
10.2 HARDWARE-BASED SIGNALING ........................................................................................49
11. PER–CHANNEL CODE GENERATION AND LOOPBACK ....................................................50
11.1 TRANSMIT SIDE CODE GENERATION ...............................................................................50
11.1.1 Simple Idle Code Insertion and Per-Channel Loopback...................................................50
11.1.2 Per-Channel Code Insertion..............................................................................................51
11.2 RECEIVE SIDE CODE GENERATION...................................................................................52
12. CLOCK BLOCKING REGISTERS................................................................................................53
13. ELASTIC STORES OPERATION .................................................................................................54
13.1 RECEIVE SIDE..........................................................................................................................55
13.2 TRANSMIT SIDE ......................................................................................................................55
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .....................................55
14.1 HARDWARE SCHEME ............................................................................................................55
14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME......................................56
14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................58
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