DS21448DK Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS21448DK

3.3V E1/T1/J1 Line Interface Design Kit Daughter Card

Dallas Semiconductor -> Maxim Integrated 

DS21448DK 3.3V E1/T1/J1 Line Interface Design Kit

General

· Upon power-up, the RCL LEDs are lit, and the INT LED is off.

· After power-up, the RCL LEDs extinguish upon external loopback.

· Due to the dual winding transformer, only the 120W line build-out (LBO) configuration setting is needed to cover

both 75W E1 and 120W E1.

Miscellaneous

· Clock frequencies are provided by a register-mapped CPLD, which is on the DS21448 daughter card.

· The definition file for this CPLD is named DS21448DK02A0_CPLD.def. See the CPLD Register Map

definitions.

Quick Setup (Register View)

· The PC loads the program, offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL

MODE. Select Register View.

· The program requests a definition file. Select DS21448DK02A0_CPLD.DEF.

· The Register View Screen appears, showing the register names, acronyms, and values. Note the CPLD def file

contains a link such that the def file for the DS21448 is also loaded. Selection among the def files is

accomplished using the drop-down box on the right-hand side of the program window.

· From the drop-down box, select the DS21448 def file and configure register CCR3 of ports 1 through 4 with a

90h.

– The device begins transmitting a pseudo-random bit sequence. Upon external loopback, the RCL LED

extinguishes, denoting that the device has found a carrier and has successfully decoded the

pseudorandom bit sequence. For more advanced configurations, please refer to the DS21448 data sheet.

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