DS2182A Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS2182A

T1 Line Monitor Chip

Maxim Integrated 

CRCCR: CRC Count Register 2

MSB

CRC7

CRC6

CRC5

CRC4

CRC3

DS2182A T1 Line Monitor Chip

CRC2

CRC1

LSB

CRC0

NAME

CRC7

CRC0

POSITION

CRCCR.7

CRCCR.0

FUNCTION

MSB of CRC6 word error count

LSB of CRC6 word error count

The CRC count register (CRCCR) is an 8-bit presettable counter that records word errors in the cyclic redundancy

check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each occurrence after

saturation if RIMR2.1 is set. The count in this register is only valid in the 193E-framing mode (RCR2.4 = 1), and is

reset and disabled in the 193S-framing mode (RCR2.4 = 0). The count is disabled during a loss-of-sync condition

(RLOS = 1).

OOFCR: OOF Count Register

MSB

OOF7

OOF6

OOF5

OOF4

OOF3

OOF2

OOF1

LSB

OOF0

NAME

OOF7

OOF0

POSITION

OOFCR.7

OOFCR.0

FUNCTION

MSB of OOF event count

LSB of OOF of event count

The OOF count register (OOFCR) is an 8-bit presettable counter that records out-of-frame (OOF) events. OOF

events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 and generates an interrupt for each

occurrence after saturation if RIMR2.2 is set. The count is disabled during a loss-of-sync condition (RLOS = 1).

FECR: Frame Error Count Register

MSB

LSB

FE7

FE6

FE5

FE4

FE3

FE2

FE1

FE0

NAME

FE7

FFE0

POSITION

FECR.7

FECR.0

MSB of frame error count

LSB of frame error count

FUNCTION

The frame error count register (FECR) is an 8-bit presettable counter that records individual frame-bit errors. In the

193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern (001011). In the 193S mode

(RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS (001110) framing patterns if RCR1.3 is

set. If RCR1.3 is cleared, then the FECR only records bit errors in the FT pattern. This 8-bit counter saturates at

255 and generates an interrupt for each occurrence after saturation if RIMR2.3 is set. The count is disabled during

a loss-of-sync condition (RLOS = 1).

7 of 26

Share Link: