DS1220Y-200 Просмотр технического описания (PDF) - Unspecified
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DS1220Y-200 Datasheet PDF : 7 Pages
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DS1220Y
16K Nonvolatile SRAM
FEATURES
.10 years minimum data retention in the absence of external
power
.Data is automatically protected during power loss
.Directly replaces 2k x 8 volatile static RAM of EEPROM
.Unlimited write cycles
.Low-power CMOS
.JEDEC standard 24-pin DIP package
.Read and write access times as fast as 100ns
.Full ±10% operating range
.Optional industrial temperature range of -40 ℃ to +85 ℃ ,
designated IND
PIN ASSIGNMENT
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10
-Address Inputs
DQ0-DQ7
-Data In/Data Out
-Chip Enable
-Write Enable
-Output Enable
Vcc
-Power (+5V)
GND
-Ground
DESCRIPTION
The DS1220Y 16K Nonvolatile SRAM is a 16, 384-bit, fully static, nonvolatile RAM organized as 2048 words by 8 bits. Each NV SRAM
has a self-contained lithium energy source and control circuitry which constantly monitors Vcc for an out-of-tolerance condition. When
such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. The NV SRAM can be used in place of existing 2K x 8 SRAMs directly conforming to the popular bytewide
24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or the 2816 EEPROM, allowing direst substitution
while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry
is required for microprocessor interfacing.
READ MODE
The DS1220Y executes a read cycle whenever (Write Enable) is inactive (high) and (Chip Enable) and (Output Enable)
are active (low). The unique address specified by the 11 address inputs (A0-A10) defines which of the 2048 bytes of data is to be
accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing the and access times are also satisfied. If and OE access times are not satisfied, then data access
must be measured from the later-occurring signal and the limiting parameter is either tCO for or tOE for rather than address
access.
WRITE MODE
The DS1220Y executes a write cycle whenever the and signals are active (low) after address inputs are stable. The
later-occurring falling earlier rising edge of or . All address inputs must be kept valid throughout the write cycle. must return
to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( and active) then
will disable the outputs in tODW from its falling edge.
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