M14128 Просмотр технического описания (PDF) - STMicroelectronics

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M14128

Memory Card IC 256/128 Kbit Serial I²C Bus EEPROM

STMicroelectronics 

M14256, M14128

Table 6. Operating Modes

Mode

Current Address Read

Random Address Read

Sequential Read

Byte Write

Page Write

Note: 1. X = VIH or VIL.

RW bit

‘1’

‘0’

‘1’

‘1’

‘0’

‘0’

WC 1

X

X

X

X

VIL

VIL

Bytes

1

1

≥1

1

≤ 64

Initial Sequence

START, Device Select, RW = ‘1’

START, Device Select, RW = ‘0’, Address

reSTART, Device Select, RW = ‘1’

Similar to Current or Random Mode

START, Device Select, RW = ‘0’

START, Device Select, RW = ‘0’

Figure 6. Write Mode Sequences with WC=0

WC

BYTE WRITE

ACK

ACK

ACK

ACK

DEV SEL

BYTE ADDR BYTE ADDR

DATA IN

R/W

WC

PAGE WRITE

WC (cont'd)

PAGE WRITE

(cont'd)

ACK

ACK

ACK

ACK

DEV SEL

BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

R/W

ACK

ACK

DATA IN N

AI01106B

byte or page write mode, the generation by the

master of the STOP condition starts the internal

memory program cycle. This STOP condition trig-

gers an internal memory program cycle only if the

STOP condition is internally decoded immediately

after the ACK bit; any STOP condition decoded

out of this "10th bit" time slot will not trigger the in-

ternal programming cycle. All inputs are disabled

until the completion of this cycle and the Memory

will not respond to any request.

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