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ST1305B

Memory Card IC 192 bit High Endurance EEPROM With Secure Logic Access Control

STMicroelectronics 

ST1305B

wise fashion for reading and programming, and in

a byte-wise fashion for internal erasing.

The device recognises three commands issued

via the RST and CLK pins (as described in the full

data sheet):

– RESET: to reset the internal address register to

00d

– READ: to increment the internal address regis-

ter, and read the data bit at that address

– PROG: to program the bit at the current ad-

dress.

The device offers two distinct configurations:

– ISSUER: for the card manufacturer, allowing

special data to be written to the chip, during ini-

tialisation

– USER: for the end user of the card, restricting

access to the chip.

Before delivery, from ST to the card issuer, the de-

vice is placed in the ISSUER configuration. This

operation is performed by blowing the “test fuse”.

Figure 2. Memory Map

000d

016d

Circuit Identification

Card Identification

16 bits

48 bits

064d

Counters / Transport Code 48 bits

EEPROM

Cells

Matrix

112d

Certificate

16 bits

In USER Configuration

READ

ONLY

READ, WRITE,

ERASE

128d

192d

Issuer Defined Area

Unused

64 bits

READ

ONLY

260d

Fuses

DS05B07

Table 2. Ordering Information Scheme

Example:

ST1305B

-

W4 /

XX YY

Delivery Form

D10 Micromodule on Super 35 mm reel

D15 Micromodule on Super 35 mm reel

W4 Wafer (180 µm thickness)

2/2

Transport Code

Given by ST

Customer Code

Given by the Issuer

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