AS4LC4M4E0 Просмотр технического описания (PDF) - Alliance Semiconductor
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AS4LC4M4E0 Datasheet PDF : 15 Pages
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March 2001
®
4Mx4 CMOS DRAM (EDO) Family
AS4LC4M4E0
AS4LC4M4E1
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Extended data out
• Refresh
- 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0
- 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3V power supply
• Industrial and commercial temperature available
Pin arrangement
SOJ
TSOP
VCC 1
I/O0 2
I/O1 3
WE 4
RAS 5
*NC/A11 6
24 GND
VCC 1
23 I/O3
I/O0 2
22 I/O2
I/O1 3
21 CAS
WE 4
20 OE
RAS 5
19 A9 *NC/A11 6
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
A10 7
A0 8
A1 9
A2 10
A3 11
VCC 12
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
A10 7
A0 8
A1 9
A2 10
A3 11
VCC 12
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
* NC on 2K refresh version; A11 on 4K refresh version
Pin designation
Pin(s)
A0 to A11
RAS
CAS
WE
I/O0 to I/O3
OE
VCC
GND
Description
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
Ground
Selection guide
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
Symbol AS4LC4M4E0/E1-50 AS4LC4M4E0/E1-60 Unit
tRAC
50
60
ns
tCAA
25
30
ns
tCAC
12
15
ns
tOEA
13
15
ns
tRC
80
100
ns
tPC
25
30
ns
ICC1
120
110
mA
ICC5
1.0
1.0
mA
4/11/01; V.1.1
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