X28HC64 Просмотр технического описания (PDF) - Renesas Electronics
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X28HC64 Datasheet PDF : 18 Pages
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X28HC64
Toggle Bit (I/O6)
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O6 will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
The Toggle Bit can eliminate the chore of saving and fetching the
last address and data in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28HC64 memories that is frequently updated. Toggle Bit Polling
can also provide a method for status checking in multiprocessor
applications. The timing diagram in Figure 5 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 6 illustrates a method for polling the Toggle Bit.
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
HIGH Z
*
* BEGINNING AND ENDING STATE OF I/O6 WILL VARY.
FIGURE 5. TOGGLE BIT BUS SEQUENCE
X28HC64
READY
LAST WRITE
YES
LOAD ACCUM
FROM ADDR N
COMPARE
ACCUM WITH
ADDR N
COMPARE
NO
OK?
YES
READY
FIGURE 6. TOGGLE BIT SOFTWARE FLOW
FN8109 Rev 4.00
June 27, 2016
Page 5 of 18
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