APA3160A Просмотр технического описания (PDF) - Anpec Electronics
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APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description (Cont.)
Left-Justified
Left-justified (LJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being
transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK is low. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines when LRCLK toggles. The data
is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.
LRCLK
SCLK
32 Clks
Left Channel
SCLK
32 Clks
Right Channel
MSB
LSB MSB
LSB
24-Bit Mode
24-Bit Mode
23 22
98
54
10
23 22
98
54
10
20-Bit Mode
20-Bit Mode
19 18
54
10
19 18
54
10
16-Bit Mode
16-Bit Mode
15 14
10
15 14
10
LRCLK
SCLK
24 Clks
Left Channel
Figure 4. Left-Justified 64 f Format
S
SCLK
24 Clks
Right Channel
MSB
24-Bit Mode
23 22
20-Bit Mode
19 18
16-Bit Mode
15 14
17 16
13 12
98
98
54
10
LRCLK
SCLK
16 Clks
Left Channel
LSB
MSB
24-Bit Mode
5 4 3 2 1 0 23 22
10
20-Bit Mode
19 18
16-Bit Mode
15 14
17 16
13 12
98
98
54
10
Figure 5. Left-Justified 48 fS Format
SCLK
16 Clks
Right Channel
LSB
54321
10
MSB
16-Bit Mode
15 14 13 12 11 10 9 8
LSB MSB
16-Bit Mode
5 4 3 2 1 0 15 14 13 12 11 10 9 8
LSB
54 32 10
Figure 6. Left-Justified 32 f Format
S
Copyright © ANPEC Electronics Corp.
13
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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