APA3160A Просмотр технического описания (PDF) - Anpec Electronics
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APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description (Cont.)
Serial Interface Control And Timing
I2S Timing
I2S timing uses LRCLK to define the data for the left channel and the right channel when the data being transmitted.
For the left channel, the LRCLK is low; for the right channel, the LRCLK is high. A bit clock running at 32, 48, or 64 × fS
is used to clock in the data. When the LRCLK signal changes state, there is a delay of one bit clock from the time which
the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP
masks unused trailing data bit positions.
32 Clks
LRCLK (Note Reversed Phase)
SCLK
Left Channel
SCLK
32 Clks
Right Channel
MSB
LSB
MSB
LSB
24-Bit Mode
24-Bit Mode
23 22
98
54
10
23 22
98
54
10
20-Bit Mode
20-Bit Mode
19 18
54
10
19 18
54
10
16-Bit Mode
16-Bit Mode
15 14
10
15 14
10
24 Clks
LRCLK (Note Reversed Phase)
SCLK
Figure 1. I2S 64 f Format
S
Left Channel
SCLK
24 Clks
Right Channel
MSB
24-Bit Mode
23 22
20-Bit Mode
19 18
16-Bit Mode
15 14
17 16
13 12
98
98
54
10
54
10
LSB
321
MSB
24-Bit Mode
0 23 22
20-Bit Mode
19 18
16-Bit Mode
15 14
17 16
13 12
98
98
54
10
LSB
54321
10
Figure 2. I2S 48 fS Format
16 Clks
LRCLK (Note Reversed Phase)
SCLK
Left Channel
SCLK
16 Clks
Right Channel
MSB
16-Bit Mode
15 14 13 12 11 10 9 8
LSB
MSB
16-Bit Mode
5 4 3 2 1 0 15 14 13 12 11 10 9 8
LSB
54321
Figure 3. I2S 32 fS Format
Copyright © ANPEC Electronics Corp.
12
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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