N386SX Просмотр технического описания (PDF) - Intel

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N386SX

Intel387™ SX MATH COPROCESSOR

Intel 

Intel387TM SX MATH COPROCESSOR

3 2 1 STATUS WORD (SW) REGISTER

The 16-bit status word (in the status register) shown

in Figure 3-2 reflects the overall state of the Math

CoProcessor It can be read and inspected by pro-

grams using the FSTSW memory or FSTSW AX in-

structions

Bit 15 the Busy bit (B) is included for 8087 compati-

bility only It always has the same value as the Error

Summary bit (ES bit 7 of status word) it does not

indicate the status of the BUSY output of the Math

CoProcessor

Bits 13–11 (TOP) serves as the pointer to the Math

CoProcessor data register that is the current Top-Of-

Stack The significance of the stack top is described

in Section 3 2 5 Data Registers

The four numeric condition code bits (C3 – C0 Bit 14

10–8) are similar to the flags in a CPU instructions

that perform arithmetic operations update these bits

to reflect the outcome The effects of the instruc-

tions on the condition code are summarized in Ta-

bles 3-1 through 3-4 These condition code bits are

used principally for conditional branching The

FSTSW AX instructions stores the Math CoProces-

sor status word directly to the CPU AX register al-

lowing the condition codes to be inspected efficient-

ly by Intel386 CPU code The Intel386 CPU SAHF

instruction can copy C3 – C0 directly to the flag bits to

simplify conditional branching Table 3-5 shows the

mapping of these bits to the Intel386 CPU flag bits

Bit 7 is the error summary (ES) status bit This bit is

set if any unmasked exception bit is set it is clear

otherwise If this bit is set the ERROR signal is

asserted

Bit 6 is the stack flag (SF) This bit is used to distin-

guish invalid operations due to stack overflow or un-

derflow from other kinds of invalid operations When

SF is set bit 9 (C1) distinguishes between stack

overflow (C1 e 1) or underflow (C1 e 0)

Bit 5 – 0 are the six exception flags of the status word

and are set to indicate that during an instruction exe-

cution the Math CoProcessor has detected one of

six possible exception conditions since these status

bits were last cleared or reset Section 3 5 entitled

Exception Handling explains how they are set and

used

The exception flags are ‘‘sticky’’ bits and can only

be cleared by the instructions FINIT FCLEX

FLDENV FSAVE and FRSTOR Note that when a

new value is loaded into the status word by the

FLDENV or FRSTOR instruction the value of ES (bit

7) and B (bit 15) are not derived from the values

loaded from memory but rather are dependent upon

the values of the exception flags (bits 5 – 0) in the

status word and their corresponding masks in the

control word If ES is set in such a case the

ERROR output of the Math CoProcessor is acti-

vated immediately

240225 – 3

ES is set if any unmasked exception bit is set cleared otherwise See Table 2-2 for interpretation of condition code

TOP values

000 e Register 0 is Top of Stack

001 e Register 1 is Top of Stack

111 e Register 7 is Top of Stack

For definitions of exceptions refer to the section entitled ‘‘Exception Handling’’

Figure 3-2 Status Word

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