AS3524 Просмотр технического описания (PDF) - austriamicrosystems AG
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AS3524 Datasheet PDF : 124 Pages
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AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
5.3.12
5.3.13
5.3.14
5.3.15
DBOP - Data Block Output Port ......................................................................................................... 73
UART – Universal Asynchronous Receiver/Transmitter.................................................................... 83
CGU - Clock generation unit .............................................................................................................. 90
CCU - Chip Control Unit .................................................................................................................. 104
6 PINOUT AND PACKAGING ...............................................................................109
6.1 Package Variants.......................................................................................................................................... 109
6.2 CTBGA180 Package Drawings ................................................................................................................... 109
6.2.1
Marking............................................................................................................................................. 109
6.2.2
CTBGA180 Package Ball-out ........................................................................................................... 110
6.2.3
CTBGA180 Ball List ........................................................................................................................ 110
6.3 Pad Cell Description..................................................................................................................................... 118
6.3.1
Digital Pads ....................................................................................................................................... 118
7 APPENDIX ..........................................................................................................119
7.1 Memory MAP ............................................................................................................................................... 119
7.2 Register definitions....................................................................................................................................... 121
7.2.1
Base Address definitions................................................................................................................... 121
8 ORDERING INFORMATION ...............................................................................122
9 COPYRIGHT .......................................................................................................123
10 DISCLAIMER ......................................................................................................123
11 CONTACT INFORMATION.................................................................................123
© 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.11
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