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FXL2SD106

Low-Voltage Dual-Supply 6-Bit Voltage Translator with Auto-Direction Sensing

ON Semiconductor 

DATA

IN

tpxx

DATA

OUT

Vmi

tpxx

VCCI

GND

VCCO

Vmo

Input tR = tF = 2.0ns, 10% to 90%

Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only

Figure 2. Waveform for Inverting and

Non-inverting Functions

OUTPUT

CONTROL

Vmi

tPZL

DATA

OUT

VY

VCCA

GND

VOL

Input tR = tF = 2.0ns, 10% to 90%

Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only

Figure 3. 3-STATE Output Low Enable Time for Low

Voltage Logic

OUTPUT

CONTROL

Vmi

tPZH

DATA

Vx

OUT

VCCA

GND

VOH

Input tR = tF = 2.0ns, 10% to 90%

Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only

Figure 4. 3-STATE Output High Enable Time for

Low Voltage Logic

Symbol

Vmi(15)

Vmo

VX

VY

Vcc

VCCI / 2

VCCO / 2

0.9 x VCCO

0.1 x VCCO

Note:

15. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).

VOUT

trise

VOH

80% x VCCO

20% x VCCO

VOL

Time

IOHD ≈ (CL +CI/O) x

∆VOUT

∆t

=

(CL

+CI/O)

x

(20%

–

80%)

tRISE

x

VCCO

Figure 5. Active Output Rise Time and Dynamic

Output Current High

VOH

tfall

VOUT

80% x VCCO

20% x VCCO

VOL

Time

IOLD ≈ (CL +CI/O) x

∆VOUT

∆t

=

(80%

(CL +CI/O) x

– 20%) x VCCO

tFALL

Figure 6. Active Output Fall Time and Dynamic

Output Current Low

tW

DATA

IN

VCCI/2

VCCI/2

Max. data rate, f = 1/tW

Figure 7. Maximum Data Rate

VCCI

GND

DATA

OUTPUT

Vmo

tskew

Vmo

VCCO

GND

tskew

DATA

OUTPUT

Vmo

VCCO

Vmo

GND

tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin)

Figure 8. Output Skew Time

© 2008 Fairchild Semiconductor Corporation

FXL2SD106 • Rev. 1.8.1

9

www.fairchildsemi.com

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