CAT24C21 Просмотр технического описания (PDF) - ON Semiconductor

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CAT24C21

1 kb Dual Mode Serial EEPROM for VESA “Plug-and-Play”

ON Semiconductor 

CAT24C21

Transmit−Only Mode: (DDC1)

Upon power−up, the CAT24C21 will output valid data

only after it has been initialized. During initialization, data

will not be available until after the first nine clocks are sent

to the device (Figure 3). The starting address for the

transmit−only mode can be determined during initialization.

If the SDA pin is high during the first eight clocks, the

starting address will be 7FH. If the SDA pin is low during the

first eight clocks, the starting address will be 00H. During

the ninth clock, SDA will be in the high impedance state.

Data is transmitted in 8 bit words with the most significant

bit first, followed by a 9th ‘don’t care’ bit which will be in

the high impedance state (Figure 4). The CAT24C21 will

continuously sequence through the entire memory array as

long as VCLK is present and no falling edges on SCL are

detected. When the maximum address (7FH) is reached,

addressing will wrap around to the zero location (00H) and

transmitting will continue. The bi−directional mode clock

(SCL) pin must be held high for the device to remain in the

transmit−only mode.

SCL

SDA

VCLK

Transmit−Only Mode Bi−Directional Mode

TVHZ

Figure 2. Mode Transition

SCL

SDA

VCLK

SCL

SDA

VCLK

SDA at high impedance for 9 clock cycles

Bit8 Bit7 Bit6 Bit5 Bit4

1 2 3 4 5 6 7 8 9 10

11 12 13 14 15

TVPU

TVAA

Figure 3. Device Initialization for Transmit−only Mode

SCL must remain high for transmit−only mode

Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Don’t Bit8 Bit7

(MSB)

(LSB) Care

TVHIGH

TVLOW

Figure 4. Transmit−Only Mode

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