HI5760 Просмотр технического описания (PDF) - Renesas Electronics
Номер в каталоге
Компоненты Описание
производитель
HI5760 Datasheet PDF : 18 Pages
| |||
HI5760
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DVDD + 0.3V
Internal Reference Output Current 50A
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
Maximum Junction Temperature
HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, IOS
Offset Drift Coefficient
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
HI5760
TA = -40oC TO 85oC
TEST CONDITIONS
MIN TYP MAX
“Best Fit” Straight Line (Note 7)
(Note 7)
(Note 7)
(Note 7)
10
-1
-0.5
-0.025
-
-
0.5
0.25
0.1
-
+1
+0.5
+0.025
-
Full Scale Gain Error, FSE
Full Scale Gain Drift
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
-10
2
+10
-10
1
+10
-
50
-
With Internal Reference (Note 7)
-
100
-
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Settling Time, (tSETT)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
(Note 3)
(Note 3)
0.2% (1 LSB, equivalent to 9 Bits) (Note 7)
0.1% (1/2 LSB, equivalent to 10 Bits) (Note 7)
RL = 25(Note 7)
Full Scale Step
Full Scale Step
IOUTFS = 20mA
IOUTFS = 2mA
2
-
20
-0.3
-
1.25
125
-
-
-
20
-
-
35
-
-
5
-
-
1.0
-
-
1.5
-
-
10
-
-
50
-
-
30
-
UNITS
Bits
LSB
LSB
% FSR
ppm
FSR/oC
% FSR
% FSR
ppm
FSR/oC
ppm
FSR/oC
mA
V
MHz
ns
ns
pV•s
ns
ns
pF
pA/ Hz
pA/ Hz
FN4320 Rev 8.00
Mar 30, 2005
Page 3 of 18
Share Link: 