CRD4525 Просмотр технического описания (PDF) - Cirrus Logic
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CRD4525 Datasheet PDF : 91 Pages
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CS4525
6.1.9 Interrupt Reporting ................................................................................................................ 48
6.1.10 Automatic Power Stage Shut-Down ................................................................................... 48
6.2 Hardware Mode ............................................................................................................................. 49
6.2.1 System Clocking ................................................................................................................... 49
6.2.2 Power-Up and Power-Down ................................................................................................. 49
6.2.2.1 Recommended Power-Up Sequence ....................................................................... 49
6.2.2.2 Recommended Power-Down Sequence .................................................................. 49
6.2.3 Input Source Selection .......................................................................................................... 50
6.2.4 PWM Channel Delay ............................................................................................................ 50
6.2.5 Digital Signal Flow ................................................................................................................ 51
6.2.5.1 High-Pass Filter ........................................................................................................ 51
6.2.5.2 Mute Control ............................................................................................................. 51
6.2.5.3 Warning and Error Reporting .................................................................................... 51
6.2.6 Thermal Foldback ................................................................................................................. 52
6.2.7 Automatic Power Stage Shut-Down ..................................................................................... 53
6.3 PWM Modulators and Sample Rate Converters ............................................................................ 53
6.4 Output Filters ................................................................................................................................. 54
6.4.1 Half-Bridge Output Filter ....................................................................................................... 54
6.4.2 Full-Bridge Output Filter (Stereo or Parallel) ........................................................................ 55
6.5 Analog Inputs ................................................................................................................................. 56
6.6 Serial Audio Interfaces ................................................................................................................... 57
6.6.1 I²S Data Format .................................................................................................................... 57
6.6.2 Left-Justified Data Format .................................................................................................... 57
6.6.3 Right-Justified Data Format .................................................................................................. 58
6.7 I²C Control Port Description and Timing ........................................................................................ 59
7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 60
7.1 Power Supply, Grounding .............................................................................................................. 60
7.1.1 Integrated VD Regulator ....................................................................................................... 60
7.2 QFN Thermal Pad .......................................................................................................................... 60
8. REGISTER QUICK REFERENCE ........................................................................................................ 61
9. REGISTER DESCRIPTIONS ................................................................................................................ 64
9.1 Clock Configuration (Address 01h) ................................................................................................ 64
9.1.1 SYS_CLK Output Enable (EnSysClk) ................................................................................... 64
9.1.2 SYS_CLK Output Divider (DivSysClk) .................................................................................. 64
9.1.3 Clock Frequency (ClkFreq[1:0]) ............................................................................................ 64
9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) ......................................................... 65
9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) .................................................................................. 65
9.1.6 Modulator Phase Shifting (PhaseShift) ................................................................................. 65
9.1.7 AM Frequency Shifting (FreqShift) ....................................................................................... 65
9.2 Input Configuration (Address 02h) ................................................................................................. 66
9.2.1 Input Source Selection (ADC/SP) ......................................................................................... 66
9.2.2 ADC High-Pass Filter Enable (EnAnHPF) ............................................................................ 66
9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only ............................................................ 66
9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) ............................................................ 66
9.3 AUX Port Configuration (Address 03h) .......................................................................................... 67
9.3.1 Enable Aux Serial Port (EnAuxPort) ..................................................................................... 67
9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) ......................................................... 67
9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) .................................................. 67
9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) ................................................. 67
9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) .................................................... 68
9.4 Output Configuration Register (Address 04h) ............................................................................... 68
9.4.1 Output Configuration (OutputCfg[1:0]) .................................................................................. 68
9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) .............................................................. 68
9.4.3 Channel Delay Settings (OutputDly[3:0]) .............................................................................. 68
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DS726A1
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