EMIF09-02726S3 Просмотр технического описания (PDF) - STMicroelectronics
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EMIF09-02726S3 Datasheet PDF : 12 Pages
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EMIF09-02726Sx
TECHNICAL INFORMATION
ESD PROTECTION
The EMIF09-02726Sx is particularly optimized to perform high level ESD protection. The clamping voltage
is given by the formula:
VCL = Vbr + Rd.IPP
The protection function is splitted in 2 stages. As shown in figure A1, the ESD strike is clamped by the first
stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a
configuration makes the output voltage very low at the Vout level.
Fig. A1: ESD clamping behavior
ESD
Surge
Vg
Rg
R
Rd
Vin
Vbr
Rd
Vout
Vbr
Rload
S1
S2
EMIF09-02726Sx
Device to be protected
To determine the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance
value Rd. Considering that : R>>Rd, Rg>>Rd and Rload>>Rd, the voltages are given by the following
formulas:
Vin
=
Rg.Vbr + Rd.Vg
Rg
Vout
=
R.Vbr
+ Rd.Vin
R
The result of the calculation made for VG= 8kV, Rg= 330 Ω (IEC1000-4-2 standard), Vbr=6.6V, Rd=0.3 Ω
and R=27 Ω is:
Vin = 13.87V
Vout = 6.75 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side because the
current involved after the resistance R is low.
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