EMIF09-02726S3 Просмотр технического описания (PDF) - STMicroelectronics
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EMIF09-02726S3 Datasheet PDF : 12 Pages
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ESD protection by the EMIF09-02726Sx
EMIF09-02726Sx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors are an ideal choice for ESD protection. They are capable of clamping the
incoming transient to a low enough level such that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operatingvoltage of the device, the TVS array becomes a low impedancepath diverting the
transient current to ground.
Fig. 7: Example of connectionfor one cell of the EMIF09-02726Sx
Logic
Transceiver
I1
I2
I3
I4
I5
GND
I6
I7
I8
EMIF09-02726Sx
I9
O1
O2
O3
O4
O5
GND
O6
O7
O8
O9
1284-A
Connector
The EMIF09-02726Sx array is the ideal board level protection of ESD sensitive semiconductor
components. It provides best efficiency when using separated inputs and outputs, in the so called 4-points
structure.
Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The EMIF09-02726Sx should be placed as near as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protectedline should be minimized.
All conductive loops, including power and ground loops should be minimized.
The ESD transient return path to ground should be kept as short as possible.
Ground planes should be used whenever possible.
Fig. 8: Recommended PCB layout to benefit from 4-point structure
Logic
Transceiver,
ASIC,...
TO DO
I1
I2
I3
I4
I5
GND
I6
I7
I8
I9
O1
O2
O3
O4
O5
GND
O6
O7
O8
O9
EMIF09-02726Sx
footprint
Logic
Transceiver,
ASIC,...
NOT TO DO
I1
I2
I3
I4
I5
GND
I6
I7
I8
I9
O1
O2
O3
O4
O5
GND
O6
O7
O8
O9
EMIF09-02726Sx
footprint
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