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854110AKILF

2.5V Differential LVDS Clock Buffer

Integrated Device Technology 

ICS854110I Data Sheet

Function Tables

Table 3A. CLK_SEL Configuration Table

Input

CLK_SEL

Operation

0

CLK0, nCLK0 is the selected reference clock

1

CLK1, nCLK1 is the selected reference clock

NOTE: CLK_SEL is an asynchronous control.

Table 3B. nOE Configuration Table

Input

nOE

Operation

0

Outputs Qx, nQx are enabled.

1

Outputs Qx, nQx are in high-impedance state.

NOTE: OE is an asynchronous control.

2.5V DIFFERENTIAL LVDS CLOCK BUFFER

Table 3C. RSET Configuration Table

RSET

Resistor Size (kΩ) Typical Output Slew Rate (V/ns)

4

0.650 (fastest)

15

0.170

50

0.150

150

0.115 (slowest)

NOTE: The RSET resistor at the ISET pin allows configuration of the

outputs to one of four pre-set output slew rates. A 5% variation of the

RSET resistor size will be tolerated.

NOTE: Slew rates are defined as ±100mV from the center of Q – nQ

signal.

Table 3D. Guaranteed Input Fail Safe Operations for CLK0, nCLK0 and CLK1, nCLK1

Input State of Selected Input

Outputs Q[0:9], nQ[0:9]

Logic Low (Selected Input: CLKx = LOW, nCLKx = HIGH)

Logic Low (Qx = LOW, nQx = HIGH)

Logic High (Selected Input: CLKx = HIGH, nCLKx = LOW)

Logic High (Qx = HIGH, nQx = LOW)

Inputs Open (Selected Input: CLKx = open, nCLKx = open)

Logic High (Qx = HIGH, nQx = LOW)

Inputs Shorted (Selected Input: CLKx shorted to nCLKx and tied to VDD)

Input Shorted (Selected Input: CLKx shorted to nCLKx and floating)

Logic High (Qx = HIGH, nQx = LOW)

Logic High (Qx = HIGH, nQx = LOW)

ICS854110AKI REVISION B JANUARY 27, 2011

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©2011 Integrated Device Technology, Inc.

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