SMJ27C010A-12J Просмотр технического описания (PDF) - Micross Components
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SMJ27C010A-12J Datasheet PDF : 13 Pages
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UVEPROM
SMJ27C010A
AS27C010A
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C010As are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from competing
outputs of the other devices. To read the output of a single
device, a low level signal is applied to the E\ and G\ pins. All
other devices in the circuit should have their outputs disabled
by applying a high-level signal to one of these pins.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C010A is a minimum of
250mA on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed circuit
board level when the devices are interfaced to industry-standard
TTL or MOS logic devices. The input/ output layout ap-
proach controls latchup without compromising performance
or packing density.
POWER DOWN
Active ICC supply current can be reduced from 30mA to 500μA
by applying a high TTL input on E\ and to 100μA by applying
a high CMOS input on E\. In this mode all outputs are in the
high-impedance state.
ERASURE
Before programming, the SMJ27C010A EPROM is erased by
exposing the chip through the transparent lid to a high- inten-
sity ultraviolet light (wavelength 2537 Å). The recommended
minimum exposure dose (UV intensity x exposure time) is 15-
W.s/cm2. A typical 12-mW/cm2, filterless UV lamp erases the
device in 21 minutes. The lamp should be located about 2.5cm
above the chip during erasure. After erasure, all bits are in the
high state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using the
SMJ27C010A, the window should be covered with an opaque
label. After erasure (all bits in logic high state), logic lows are
programmed into the desired locations. A programmed low
can be erased only by ultraviolet light.
SNAP! PULSE PROGRAMMING
The SMJ27C010A is programmed by using the SNAP! Pulse
programming algorithm as illustrated by the flow chart (Figure
1). This algorithm programs in a nominal time of thirteen
seconds. Actual programming time varies as a function of the
programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse
of 100 microseconds (μs) followed by a byte verification to
determine when the addressed byte has been successfully
programmed. Up to ten 100μs pulses per byte are provided
before a failure is recognized.
The programming mode is achieved when VPP = 13V, VCC=
6.5V, E\ = VIL, and G\ = VIH. Data is presented in parallel
(eight bits) on pins DQ0 through DQ7. Once addresses and
data are stable, PGM\ is pulsed low.
More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in
any order. When the SNAP! Pulse programming routine is
complete, all bits are verified with VCC = VPP = 5V ± 10%.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
inputs on the E\ or the PGM\ pins.
PROGRAM VERIFY
Programmed bits can be verified with VPP = 13V when G\ =
VIL, and E\ = VIL, and PGM\ = VIH.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and type. This mode is activated
when A9 (pin 26) is forced to 12V. Two identifier bytes are
accessed by toggling A0. All other addresses must be held low.
The signature code for these devices is 97D6. A0 low selects
the manufacturer’s code 97 (Hex), and A0 high selects the
device code D6 (Hex), as shown in Table 2.
TABLE 2. SIGNATURE MODES
IDENTIFIER*
PINS
A0
DQ7 DQ6 DQ5 DQ4 DQ3
MANUFACTURER CODE
VIL
1
0
0
1
0
DEVICE CODE
VIH
1
1
0
1
0
* E\ = G\ = VIL, A1 - A8 = VIL, A9 = VH, A10 - A16 = VIL, VPP = VCC.
DQ2
1
1
DQ1
1
1
DQ0
1
0
HEX
97
D6
SMJ27C010A
AS27C010A
Rev. 2.6 01/10
Micross Components reserves the right to change products or specifications without notice.
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