AS29F040DCG-70/Q Просмотр технического описания (PDF) - Micross Components
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AS29F040DCG-70/Q Datasheet PDF : 27 Pages
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FLASH
AS29F040
has completed the program or erase operation. The system can
read array data on DQ7-DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section on
DQ5). If it is, the system should then determine again whether
the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program
or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit it toggling and DQ5 has not gone
high. The system may continue to monitor the toggle bit and
DQ5 through successive read cycles, determining the status
as described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1.” This is a failure condition
that indicates the program or erase cycle was not successfully
completed.
The DQ5 failure condition may appear if the system tries
to program a “1” to a location that is previously programmed to
“0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, DQ5 produces a
“1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply to
the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional
sector erase command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the time between additional sector
erase commands will always be less than 50μs. See also the
“Sector Erase Command Sequence” section.
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data\ Polling) or DQ6
(Toggle Bit I) to ensure the device has accepted the command
sequence, and then read DQ3. If DQ3 is “1”, the internally
controlled erase cycle has begun; all further commands (other
than Erase Suspend) are ignored until the erase operation is
complete. If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been accepted,
the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3
is high on the second status check, the last command might not
have been accepted. Table 5 shows the outputs for DQ3.
TABLE 5: WRITE OPERATION STATUS
OPERATION
DQ71
Standard Embedded Program Algorithm
Mode
Embedded Erase Algorithm
DQ7\
0
DQ6
Toggle
Toggle
DQ52
0
0
DQ3
0
1
DQ21
No Toggle
Toggle
Erase Reading within Erase Suspended Sector
1 No toggle 0
N/A Toggle
Suspend Reading within Non-Erase Suspended Sector
Mode
Erase-Suspend-Program
Data
DQ7\
Data
Toggle
Data
0
Data
N/A
Data
N/A
NOTES:
1. DQ7 and DQ2 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeding Timing
Limits” for more information.
AS29F040
Rev. 2.3 01/10
12
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