SM1350AAQM Просмотр технического описания (PDF) - Nippon Precision Circuits

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SM1350AAQM

High Tone Quality Melody IC

Nippon Precision Circuits  

SM1350AAQM

The melody selection in serial mode is controlled by S0 and S1 as shown in the following table. The states of S0 and S1

are read in immediately after startup and the change of S0 and S1 during melody output is invalid.

S1

LOW

HIGH

HIGH

STN

S0

Melody counter

-

Increments when melody output stops

LOW

No increment

HIGH

Increments when melody output starts

Stable 1. S0, S1 resistor and melody counter

S1

S0

Selection Counter

#N

#N+1

#N+2

#N+2

Melody Output

(SP pin)

#N

#N+1

#N+2

#N+2

Figure 10. S0, S1 melody output control timing

STOP pin

One-shot output mode stops when STOP goes from HIGH to LOW. The STOP input is ignored in level hold output

mode and is also ignored in one-shot mode when STN is LOW. Note that even when STOP is LOW, STN has higher

priority.

CT pin

A pulse in sync with selected notes or rests is output on CT. 16.4ms pulse is output when a note or rest occurs for which

the corresponding CT data in score ROM is set to 1.

q

e e q.

eq

CT DATA 1

CT

1

0

1

10

Figure 11. CT pulse mode output

Fast Damping

When melody output stops, the D/A converter output amplitude dose not fall to zero instantaneously, instead the output

converges to zero within a maximum of 8.2ms to prevent noise being generated. Also, when one-shot melody output

mode is retriggered, melody output restarts after the fast damping interval. When melody out is stopped by ICN input, it

instantaneously becomes 0 level.

STOP

Melody Output

(SP pin)

Figure 12. Fast damping timing

8.2msec

SEIKO NPC CORPORATION - 11

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