Low-Voltage, CMOS Analog Multiplexers/Switches
with Enable Inputs and Address Latching
______________________________________________Test Circuits/Timing Diagrams
V+
VADD_
50Ω
V+
LE V+
ADDC
NO0
ADDB
NO1–NO6
ADDA
NO7
COM
MAX4530
EN2
EN1
GND
V-
V-
V+
+3V
-3V
300Ω
VOUT
35pF
VADD_
50Ω
V+
LE V+
ADDA
NO0
ADDB
NO1_, NO2_
NO3_
MAX4531 COM
EN2
EN1
GND V-
V-
V+
+3V
-3V
300Ω
VOUT
35pF
VADD_
50Ω
V+
LE V+
ADD_
NO_
NC_
MAX4532 COM
EN2
EN1
GND V-
V-
+3V
-3V
300Ω
VOUT
35pF
V+
VADD_
50%
0V
VNO0
VOUT 0V
90%
VNO7
tTRANS
V+
50%
VADD_
0V
VNO0
VOUT 0V
90%
VNO3
tTRANS
V+
VADD_
50%
0V
VNC_
VOUT 0V
90%
VNO_
tTRANS
90%
tTRANS
90%
tTRANS
90%
tTRANS
Figure 1. Address Transition Time
10 ______________________________________________________________________________________