SSC2005SC Просмотр технического описания (PDF) - Sanken Electric co.,ltd.
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SSC2005SC Datasheet PDF : 19 Pages
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SSC2005SC
The value of RRT should set larger than RRT(SET).
RRT(SET) is given by tON(MAX)_OP in Figure 8-7.
The range of RRT is 15 kΩ to 47 kΩ. When tON(MAX)_OP
is 16.3 μs or less, RRT is set 15 kΩ. If tON(MAX)_OP is
45 μs or more, RRT is over 47 kΩ. Thus, the setting
value of fSW(SET) in Equation (5) is increased and the
value of LP should be calculated again.
If the setting value of RRT is too large for RRT(SET), it is
necessary to be careful about the audible noise of
transformer in the transient operation including
startup.
50
45
40
35
30
tON(MAX)_OP
25
20
15
ex. Range of RRT Setting
10
5
0
RRT(SET)
15 20 25 30 35 40 45 50
RRT (kΩ)
Figure 8-7 tON(MAX) as a function of RRT (IC design)
8.5 Zero Current Detection and Bottom-on
Timing (Delay Time) Setting
Figure 8-8 shows the peripheral circuit of the RDLY
pin and the CS pin. Figure 8-9 shows the waveform of
each pin.
The off-time and the bottom on timing of VDS are set
by both zero current detection of inductor current, IL and
the delay time.
The off-time of a power MOSFET is set by the zero
current detection signal of the CS pin and the delay time
of the RDLY pin.
Thus, simple PFC circuit with inductor having no
auxiliary winding is realized.
The zero current detection signal of inductor current,
IL, is detected by RCS and it is inputted to the CS pin as
shown in Figure 8-8. While the power MOSFET is in
OFF state, the CS pin voltage decrease to the absolute
value of Zero Current Detection Threshold Voltage,
VCS(ZCD) = − 10 V, or less, the OUT pin outputs ON
signal after the turn-on delay time, tDLY.
The value of tDLY is determined by the value of the
resistor, RDLY, connected to the RDLY pin.
Figure 8-10 shows relationship between RDLY value
and .tDLY value (IC design). As shown in Figure 8-11, the
value of RDLY adjusts the turn-on timing to the bottom
point of VDS free oscillation waveform on actual
operation in the application.
Adjusting the output timing of the on signal to the
bottom point of VDS free oscillation waveform
(quasi-resonant operation), low noise, low switching loss
and high efficiency PFC circuit is realized.
The range of RDLY is 15 kΩ to 56 kΩ. The ideal delay
time shown in figure 8-11 is given by Equation (3), and
it depends on LP and CV.
t ONDLY ≒ LP CV (s)
(3)
where,
LP : Inductance value of the result of Equation (5).
CV : Sum of the following capacitance: the output
capacitance of power MOSFET, the parasitic
capacitance of inductor, and the junction capacitance
of boost diode.
IL
D1
VOUT
L1
Q1
7
ID
OUT
U1
C1
ZCD COMP
VCS(ZCD)= －10mV
OSC
RCS
R4
CS
5
RT RDLY GND
34
6
C5 DZCS RRT C3 RDLY C4
Figure 8-8 The peripheral circuit of the RDLY pin
and the CS pin
VDS
0
ID
0
OUT pin voltage
0
IL
0
CS pin voltage
0
VZCD
Turn on delay time, tDLY
Figure 8-9 Zero current detection waveform
SSC2005SC-DS Rev.1.1
SANKEN ELECTRIC CO.,LTD.
10
Feb. 06, 2015
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