MAX3673 Просмотр технического описания (PDF) - Microsemi Corporation
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MAX3673 Datasheet PDF : 17 Pages
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Low-Jitter Frequency Synthesizer
with Selectable Input Reference
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1)
Reference Clock Frequency
fREF
Reference Clock Frequency
Tolerance
MIN TYP MAX UNITS
Table 1
-200
+200
MHz
ppm
Reference Clock Duty Cycle
40
60
%
Reference Clock Amplitude
Detection Assert Threshold
VDT
Differential swing (Notes 5, 6)
200
mVP-P
LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 7)
Output High Voltage
VOH
VCC - VCC - VCC -
V
1.13 0.98 0.83
Output Low Voltage
VOL
VCC - VCC - VCC -
V
1.85 1.70 1.55
Differential-Output Swing
Output Current When Disabled
Output Frequency
fOUT
VO = VCC - 2.0V to VCC - 0.7V
1.1 1.45 1.8
130
Tables
2, 3
VP-P
μA
MHz
Output Rise/Fall Time
Output Duty Cycle
tR, tF
Output-to-Output Skew
tSKEW
OTHER AC ELECTRICAL SPECIFICATIONS
PLL Jitter Transfer Bandwidth
Jitter Peaking
PFD Compare Frequency
VCO Center Frequency
Random Jitter Generation
Determinisitic Jitter Caused by
Power-Supply Noise
20% to 80% (Note 8)
PLL_BYPASS = 0
PLL_BYPASS = 1 (Note 9)
Within output bank
All outputs
Integrated 12kHz to 20MHz (Notes 5, 8)
(Note 10)
150
500
ps
48
52
%
45
55
20
ps
40
40
kHz
0.1
dB
61.44
MHz
2.457
GHz
0.3
1.0 psRMS
5
psP-P
Frequency Difference Between
Reference Clock and VCO
Within Which the PLL is
Considered in Lock
500
ppm
Frequency Difference Between
Reference Clock and VCO at
Which the PLL is Considered
Out-of-Lock
PLL Lock Time
tLOCK Figure 2
800
ppm
600
μs
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