MAX3674 Просмотр технического описания (PDF) - Microsemi Corporation

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MAX3674

High-Performance, Dual-Output, Network Clock Synthesizer

Microsemi Corporation 

High-Performance, Dual-Output,

Network Clock Synthesizer

independent I2C transactions. Alternatively, small fre-

quency changes can be made in one step using the

increment and decrement commands.

The following are three examples using the serial I2C

interface.

Example 1: Set the synthesizer frequency.

1) Write the PLL_L and PLL_H registers with a valid

configuration.

2) Write the LOAD command to update the PLL

dividers with the current PLL_L, PLL_H content.

Example 2: Read the synthesizer frequency.

1) Write the GET command to update the PLL_L,

PLL_H registers with the PLL divider settings.

2) Read the PLL_L, PLL_H registers through I2C

protocol.

Example 3: Change the synthesizer frequency in

small steps.

1) Write the INC or DEC command to change the

synthesizer frequency by granularity step G.

The ID register is read only, used for the purpose of

identification. When a read command is sent to the

MAX3674, the content in ID is sent back to the con-

troller together with the data in PLL_L and PLL_H, so a

system can use this information accordingly. See

Table 11.

When changing parallel mode into serial mode, at the

rising edge of PLOAD input, the MAX3674 internal reg-

ister contents and frequency divider configurations are

not changed until rewritten by the user through the seri-

al I2C interface. However, when changing serial mode

into parallel mode, at the falling edge of PLOAD input,

the internal register contents and frequency divider

configurations immediately reflect the logic state of the

hardwired pins (M[9:0], NA[2:0], NB, and P).

Register Read/Write Transfer

Write Mode (R/W = 0)

The host controller writes the configuration registers by

initiating a write transfer with the MAX3674 slave

address (first byte), followed by the address of the con-

figuration register (second byte: 0x00, 0x01, or 0xF0),

and the configuration data byte (third byte). This trans-

fer can be followed by writing more registers by send-

ing the configuration register address followed by one

data byte. The MAX3674 acknowledges each byte sent

by the host controller. The transfer ends by a stop bit

sent by the host controller. The number of configuration

data bytes and the write sequence are not restricted.

Table 10 shows an example of the complete configura-

tion register write transfer.

Read Mode (R/W = 1)

The host controller reads the configuration registers by

initiating a read transfer. The MAX3674 supports read

transfer immediately after the first byte without a change

in the transfer direction. Immediately after the host con-

troller sends the slave address, the MAX3674 acknowl-

edges and then sends the configuration registers and

identification (PLL_L , PLL_H, and ID) back-to-back to

the host controller. The CMD register cannot be read. To

read the two configuration registers and the current PLL

settings, the user can read PLL_L and PLL_H, write the

GET command (loads the current configuration into

PLL_L and PLL_H), and read PLL_L and PLL_H again.

Table 11 shows the complete register read transfer.

Note that the PLL_L and PLL_H registers and divider

settings may not be equivalent after the following exam-

ple cases:

• Writing the INC command.

• Writing the DEC command.

• Writing the PLL_L, PLL_H registers with a new con-

figuration and not writing the LOAD command.

Table 10. Configuration Register Write Transfer

1

7

1

1

8

1

8

1

8

1

8

1

1

BIT

BITS

BIT

BIT

BITS

BIT

BITS

BIT

BITS

BIT

BITS

BIT

BIT

Start

Slave

Address

R/W

ACK &PLL_H ACK

Config-

Byte 1

ACK

&PLL_L

ACK

Config-

Byte 2

ACK

Stop

— 10110xx 0

—

0x01

—

Data

—

0x00

—

Data

—

—

M

M

M

S

M

S

M

S

M

S

M

S

M

M = master, S = slave.

14 ______________________________________________________________________________________

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