2SK3901 Просмотр технического описания (PDF) - Renesas Electronics

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2SK3901

SWITCHING N-CHANNEL POWER MOS FET

Renesas Electronics 

2SK3901

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

Gate Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

IGSS

VGS = ±20 V, VDS = 0 V

Gate Cut-off Voltage

Forward Transfer Admittance Note

Drain to Source On-state Resistance Note

VGS(off)

| yfs |

RDS(on)1

VDS = 10 V, ID = 1 mA

VDS = 10 V, ID = 30 A

VGS = 10 V, ID = 30 A

RDS(on)2 VGS = 4.5 V, ID = 30 A

Input Capacitance

Ciss

VDS = 10 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

VDD = 30 V, ID = 30 A

Rise Time

tr

VGS = 10 V

Turn-off Delay Time

td(off)

RG = 0 Ω

Fall Time

tf

Total Gate Charge

QG

VDD = 48 V

Gate to Source Charge

QGS

VGS = 10 V

Gate to Drain Charge

Body Diode Forward Voltage Note

QGD

VF(S-D)

ID = 60 A

IF = 60 A, VGS = 0 V

Reverse Recovery Time

Reverse Recovery Charge

trr

IF = 60 A, VGS = 0 V

Qrr

di/dt = 100 A/µs

Note Pulsed

MIN.

1.5

18

TYP.

2.0

36

10.3

12.1

1950

380

150

12

6

48

5.0

40

7.5

10.0

0.96

32

45

MAX.

10

±10

2.5

13

16.5

1.5

UNIT

µA

µA

V

S

mΩ

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

V

ns

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = 20 → 0 V

BVDSS

IAS

ID

VDD

VDS

Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

RG

PG.

VGS

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

RL

VDD

VGS

VGS

Wave Form

10%

0

VDS

90%

VDS

VDS

0

Wave Form

td(on)

VGS

90%

90%

10% 10%

tr td(off) tf

ton

toff

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D17176EJ1V0DS

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