SK100EP111 Просмотр технического описания (PDF) - Semtech Corporation
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SK100EP111 Datasheet PDF : 4 Pages
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SEMTECH
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Low-Voltage 1:10 Differential
ECL/PECL/HSTL Clock Driver
SK100EP111
Preliminary Information
This document contains information on a new product. The
parametric information, although not fully characterized, is the result
of testing initial devices.
Features
• 100 ps Part-to-Part Skew
• 35 ps Output-to-Output Skew
• Differential Design
• VBB Output
• Low Voltage VEE Range of –2.375 to –3.8V for ECL
• Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL
• 75 KΩ Input Pulldown Resistors
• ECL/PECL Outputs
Description
The SK100EP111 is a low skew 1-to-10 diffferential driver, designed
with clock distribution in mind. It accepts two clock sources into an
input multiplexer. The ECL/PECL input signals can be either
differential or single-ended if the VBB output is used. HSTL inputs
can be used when the EP111 is operating under PECL conditions.
The selected signal is fanned out to 10 identical differential outputs.
The SK100EP111 is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and characterization is
used to determine process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50Ω,
even if only one side is being used. In most applications, all ten
differential pairs will be used and therefore terminated. In the case
where fewer than ten pairs are used, it is necessary to terminate at
least the output pairs on the same package side as the pair(s) being
used on that side in order to maintain minimum skew. Failure to do
this will result in small degradations of propagation delay (on the
order of 10–20 ps) of the output(s) being used which, while not
being catastrophic to most designs, will mean a loss of skew margin.
The SK100EP111, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the EP111
to be used for high performance clock distribution in +3.3V or +2.5V
systems. Designers can take advantage of the EP111’s performance
to distribute low skew clocks across the backplane or the board. In
a PECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies.
October 4, 1999
Low-Voltage 1:10
Differential ECL/PECL/HSTL
Clock Driver
32 Lead
LQFP Package
Logic Symbol
CLK0
CLK0*
CLK1
CLK1*
CLK_SEL
10
0
1
VBB
Q0:9
Q0*:9*
Pinout
VCC0
Q2*
Q2
Q1*
Q1
Q0*
Q0
VCC0
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
SK100EP111
29
12
30
11
31
10
32
9
12 34 56 7 8
VCC0
Q7
Q7*
Q8
Q8*
Q9
Q9*
VCC0
Pin Names
Pin
Function
CLK0, CLK0*
CLK1, CKL1*
Q0:9, Q0*:9*
CLK_SEL
VBB
Differential ECL/PECL Input Pair
Differential HSTL Input Pair
Differential PECL Outputs
Active Clock Select Input
VBB Output
Function
CLK_SEL
0
1
Active Input
CLK0, CLK0*
CLK1, CLK1*
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