PHE13005 Просмотр технического описания (PDF) - Unspecified

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PHE13005

Silicon diffused power transistor

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WeEn Semiconductors

PHE13005

Silicon diffused power transistor

Ptot

Pder(%) = Ptot(25°C) ×100%

Fig. 3. Normalized total power dissipation as a function of heatsink temperature

Th ≤ 25 °C

Mounted with heatsink compound and (30 ± 5) N force on the centre of the envelope

(1) Ptot maximum and Ptot peak maximum lines

(2) Second breakdown limits

(3) Region of permissible DC operation

(4) Extension of operating region for repetitive pulse operation

(5) Extension of operating region during turn-on in single transistor converters provided that RBE ≤ 100 Ω and

tp ≤ 0.6 μs

Fig. 4. Forward bias safe operating area

PHE13005

Product data sheet

All information provided in this document is subject to legal disclaimers.

30 March 2018

© WeEn Semiconductors Co., Ltd. 2018. All rights reserved

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