PEB2047 Просмотр технического описания (PDF) - Siemens AG
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PEB2047 Datasheet PDF : 50 Pages
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PEB 2047
PEB 2047-16
For a 8 MHz/8 MHz-system for example the following frame delay table can be deduced from the
timing diagram:
Table 10
Frame Delay
IN0 ... IN4 or
(IN4 ... IN7
switched to
OUT1 ... OUT3)
IN4 ... IN7
switched to
OUT0
Delay/Number of
frames
Input Time-Slot
0– 1
2– 3
4– 5
.
.
.
118 – 119
120 – 121
122 – 123
124 – 125
126 – 127
0– 1
2– 3
4– 5
.
.
.
120
121
122 – 123
124 – 125
126 – 127
Switched to Output Time-Slot
6 – 127
8 – 127
10 – 127
.
.
.
124 – 125
126 – 127
–
–
–
0– 5
0– 7
0– 9
.
.
.
0 – 123
0 – 125
0 – 127
2 – 127
4 – 127
7 – 127
9 – 127
11 – 127
.
.
.
127
–
–
–
–
0– 6
0– 8
0 – 10
.
.
.
0 – 126
0 – 127
1 – 127
3 – 127
5 – 127
0
1
–
–
.–
.
.
.
–
–
–
0– 1
0– 3
–
–
–
.
.
.
–
.–
0
0– 2
0– 4
2
Semiconductor Group
49
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