PEB2047 Просмотр технического описания (PDF) - Siemens AG
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PEB2047 Datasheet PDF : 50 Pages
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PEB 2047
PEB 2047-16
6 Applications
6.1 Determination of MTSL Frame Delay
When switching time slots from the input of the MTSL to its output, the question often arises whether
the incoming channel is transmitted in the same frame (0 frame delay), the next frame (1 frame
delay), or even in the frame thereafter (2 frames delay).
Because framing delay is different depending on the selected output port, delay timings have to be
calculated separately for all outputs.
The following text advises how to do this calculation and delivers a value for MINIMAL or
CONSTANT delay. A CONSTANT delay may be programmed by the control byte bit D12 of IAR-
register.
Instructions for Use
1. Determine the data rate for the input data stream and for the output data stream. e.g. 4 Mbit/s for
input data stream; 4 Mbit/s for output data stream.
2. Select a device clock. Please note, that not all ouput ports are available for every choice of the
device clock (refer to the following table) !! e.g. 8 MHz.
3. Determine the constant Td for your special configuration by selecting the corresponding row in
the table below (a, b, c or d):
e.g. for a 4 Mbit/s input- /output- data stream with 8 MHz device clock row a) has to be selected.
The table delivers a value Td = 4 for line OUT0 and Td = 3 for OUT1 … 7.
A big value for Td also means a big internal switching delay.
Input Data Output Data Device
Td for Td for
Rate [Mbit/s] Rate [Mbit/s] CLK [MHz] OUT0 OUT1
a) 2, 41)
2
4, 8
4
4
4
3
8
b) 2, 41)
4
4, 8
8
4
7
6
8
c) 2
4
4, 8, 16
8
8
6
5
16
d) 2, 41)
8
4, 8, 16
16
8
11
10
16
Td for
Td for
OUT2 … 3 OUT4 … 7
3
3
6
not available !!
5
5
10
not available !!
1) 2, 4 has the meaning 2,048 Mbit/s or 4,096 Mbit/s
Semiconductor Group
44
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