HC2510C Просмотр технического описания (PDF) - Hynix Semiconductor

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HC2510C

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

Hynix Semiconductor 

HC2510C

Table 6. Switching Characteristics Over Recommended Ranges of Supply

Voltage and Operating Free-air Temperature. (CL=30pF) =

Parameter From(Input) TO(Output)

tphase error ♣

tsk

66MHz < CLKIN↑<

100MHz

CLKIN↑ = 100MHz

Any Y of FBOUT

Jitter(pk-pk)

Duty

Cycle

tr

CLKIN > 66MHz

CLKIN > 66MHz

tf

=These parameters are not production tested.

♣ Phase error does not include jitter.

FBIN↑

FBIN↑

Any Y or

FBOUT

Any Y or

FBOUT

Any Y or

FBOUT

Any Y or

FBOUT

Any Y or

FBOUT

VCC = 3.3V

±0.165V

VCC =

3.3V±0.3V

Unit

Min Typ Max Min Typ Max

150

150

ps

-50

50

ps

200 ps

-100

100 ps

45

55 %

1.3 1.9 0.8

2.1 ns

1.7 2.5 1.2

2.7 ns

Figure 1. Load Circuit and Voltage Waveforms

From Output Under Test

30pF

Load Circuit For Outputs

Input

500§Ù

tpd

50% VCC

Output

0.4V

tr

2V

50% V CC

tf

2V

0.4V

Voltage Waveforms

Propagation Delay Times

Notes: 1. All input pulses are supplied by generators having

the following characteristics: PRR ≤ 100MHz, Zo

=50Ω, tr =1.2ns, tf=1.2ns

2.The outputs are measured one at a time with one

transition per measurement.

3V

0V

VOH

VOL

5

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