CXL1512M Просмотр технического описания (PDF) - Sony Semiconductor

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Компоненты Описание

производитель

CXL1512M

CCD Delay Line for NTSC

Sony Semiconductor 

Recommended Clock Conditions (Ta = 25*C)

• Input clock amplitude

VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.)

• Clock frequency

fCLK 3.579545MHz

• Input clock waveform

sine wave

Input Signal Amplitude

Vsig

350mVp-p (Typ.), 575mVp-p (Max.)

Block Diagram and Pin Configuration (Top View)

CXL1512M

24

23

22

21

20

19

18

17

16

15

14

13

Autobias

circuit (C)

fsc buffer

D

1H + D

Output

circuit (S/H)

PLL

Timing

Driver

φ1

Autobias

circuit (Y)

Driver

φ2

Bias circuit

Bias circuit

Clamp circuit

1H

Output

circuit (S/H)

1

2

3

4

5

6

7

8

9

10

11

12

–2–

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