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MICRF001BN Просмотр технического описания (PDF) - Micrel

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MICRF001BN Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MICRF001
3. CAGC Pin
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5. REFOSC Pin
Micrel
Figure 3 illustrates the CAGC pin interface circuit. The AGC
control voltage is developed as an integrated current into a
capacitor CAGC. The attack current is nominally 15µA,
while the decay current is a 1/10th scaling of this,
approximately 1.5µA. Signal gain of the RF/IF strip inside
the IC diminishes as the voltage on CAGC decreases. By
simply adding a capacitor to CAGC pin, the attack/decay
time constant ratio is fixed at 1:10. Further discussion on
setting the attack time constant is found in “Application Note
22, MICRF001 Theory of Operation”, section 6.5.
Modification of the attack/decay ratio is possible by adding
resistance from CAGC pin either to VDDBB or VSSBB, as
desired.
4. DO Pin
The output stage for the Data Comparator (DO pin) is shown
in Figure 4. The output is a 10µA push-10µA pull, switched
current stage. Such an output stage is capable of driving
CMOS-type loads.
The REFOSC input circuit is shown in Figure 5. Input
impedance is quite high (200k). This is a Colpitts oscillator,
with internal 30pF capacitors. This input is intended to work
with standard ceramic resonators, connected from this pin to
VSSBB. The resonators should not contain integral
capacitors, since these capacitors are contained inside the
IC. Externally applied signals should be AC-coupled,
amplitude limited to approximately 0.5Vpp. The nominal DC
bias voltage on this pin is 1.4V.
6. Control Inputs (SEL0, SEL1, SWEN)
Control input circuitry is shown in Figure 6. The standard
input is a logic inverter constructed with minimum geometry
MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large
channel length device which functions essentially as a
“weak” pullup to VDDBB. Typical pullup current is 5µA,
leading to an impedance to the VDDBB supply of typically
1M.
Figure 2 CTH Pin
Figure 3 CAGC Pin
Figure 4 DO Pin
June 1998
Figure 5 REFOSC Pin
7
Figure 6 SEL0, SEL1, SWEN
MICRF001

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