MK2049-36 Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK2049-36 Datasheet PDF : 10 Pages
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PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
MK2049-36 Output Decoding Table – External Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK
8K
Crystal
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
0 0 0 0 1.544 3.088 8 kHz
0 0 0 1 2.048 4.096 8 kHz
0 0 1 0 22.368 44.736 8 kHz
0 0 1 1 17.184 34.368 8 kHz
0 1 0 0 77.76 155.52 8 kHz
0 1 0 1 16.384 32.768 8 kHz
0 1 1 0 14.352 28.704 8 kHz
0 1 1 1 TEST TEST TEST
1 0 0 0 18.528 37.056 8 kHz
1 0 0 1 12.352 24.704 8 kHz
1 0 1 0 7.68
15.36 8 kHz
1 0 1 1 TEST TEST TEST
1 1 0 0 12.288 24.576 8 kHz
1 1 0 1 16.384 32.768 8 kHz
12.352
12.288
11.184
11.456
19.44
16.384
14.352
TEST
18.528
24.704
15.36
TEST
24.576
12.288
MK2049-36 Output Decoding Table – Buffer Mode (MHz)
ICLK
22 - 36
11 - 18
FS3 FS2 FS1 FS0 CLK/2 CLK
8K
1 1 1 0 ICLK/2 ICLK N/A
1 1 1 1 2*ICLK 4*ICLK N/A
Crystal
ICLK/2
ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
MDS 2049-36 A
4
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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