FW801A-DB Просмотр технического описания (PDF) - Agere -> LSI Corporation
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FW801A-DB Datasheet PDF : 24 Pages
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Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Signal Information (continued)
Table 1. Signal Descriptions (continued)
Pin
28
32
5, 16, 22,
39
25, 33, 34
12, 15, 21,
40, 47
26, 27, 35,
36
43
44
Signal*
TPB0−
TPBIAS0
VDD
VDDA
VSS
VSSA
XI
XO
Type
Name/Description
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias
voltage needed for proper operation of the twisted-pair cable drivers and
receivers and for sending a valid cable connection signal to the remote
nodes.
—
Digital Power. VDD supplies power to the digital portion of the device.
—
Analog Circuit Power. VDDA supplies power to the analog portion of the
device.
—
Digital Ground. All VSS signals should be tied to the low-impedance
ground plane.
—
Analog Circuit Ground. All VSSA signals should be tied together to a low-
impedance ground plane.
—
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant
fundamental mode crystal. Although, when a 24.576 MHz clock source is
used, it can be connected to XI with XO left unconnected. The optimum
values for the external shunt capacitors are dependent on the specifica-
tions of the crystal used. It is suggested that two 12 pF shunt capacitors
be used for a crystal with a specified 7 pF loading capacitance. For more
details, see Crystal Selection Considerations in the Application Informa-
tion section.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Agere Systems Inc.
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