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FW801A-DB

Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet, Rev. 1

June 2001

FW801A Low-Power PHY IEEE 1394A-2000

One-Cable Transceiver/Arbiter Device

Description (continued)

The SYSCLK output will become active (and the PHY/

link interface will be initialized and become operative)

within 3 ms after LPS is asserted high, when the

FW801A is in the low-power mode.

Two of the signals are used to set up various test con-

ditions used in manufacturing. These signals (SE and

SM) should be connected to VSS for normal operation.

CPS

LPS

/ISO

CNA

SYSCLK

LREQ

CTL0

CTL1

D0

D1

D2

D3

D4

D5

D6

D7

C/LKON

SE

SM

PD

/RESET

LINK

INTERFACE

I/O

RECEIVED

DATA

DECODER/

RETIMER

ARBITRATION

AND

CONTROL

STATE

MACHINE

LOGIC

BIAS

VOLTAGE

AND

CURRENT

GENERATOR

CABLE PORT 0

TRANSMIT

DATA

ENCODER

CRYSTAL

OSCILLATOR,

PLL SYSTEM,

AND

CLOCK

GENERATOR

Figure 1. Block Diagram

R0

R1

TPA0+

TPA0–

TPBIAS0

TPB0+

TPB0–

XI

XO

5-5459.e (F)r.2

Agere Systems Inc.

5

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