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FW801A-DB

Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet, Rev. 1

June 2001

FW801A Low-Power PHY IEEE 1394A-2000

One-Cable Transceiver/Arbiter Device

Description

The Agere Systems Inc. FW801A device provides the

analog physical layer functions needed to implement a

one-port node in a cable-based IEEE 1394-1995 and

IEEE 1394a-2000 network.

The cable port incorporates two differential line trans-

ceivers. The transceivers include circuitry to monitor

the line conditions as needed for determining connec-

tion status, for initialization and arbitration, and for

packet reception and transmission. The PHY is

designed to interface with a link-layer controller (LLC).

The PHY requires either an external 24.576 MHz crys-

tal or crystal oscillator. The internal oscillator drives an

internal phase-locked loop (PLL), which generates the

required 400 MHz reference signal. The 400 MHz ref-

erence signal is internally divided to provide the

49.152 MHz, 98.304 MHz, and 196.608 MHz clock sig-

nals that control transmission of the outbound encoded

strobe and data information. The 49.152 MHz clock

signal is also supplied to the associated LLC for syn-

chronization of the two chips and is used for resynchro-

nization of the received data. The powerdown function,

when enabled by the PD signal high, stops operation of

the PLL and disables all circuitry except the cable-not-

active signal circuitry.

The PHY supports an isolation barrier between itself

and its LLC. When /ISO is tied high, the link interface

outputs behave normally. When /ISO is tied low,

internal differentiating logic is enabled, and the outputs

become short pulses, which can be coupled through a

capacitor or transformer as described in the

IEEE 1394-1995 Annex J. To operate with bus-keeper

isolation, the /ISO pin of the FW801A must be tied

high.

Data bits to be transmitted through the cable ports are

received from the LLC on two, four, or eight data lines

(D[0:7]), and are latched internally in the PHY in

synchronization with the 49.152 MHz system clock.

These bits are combined serially, encoded, and

transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or

393.216 Mbits/s as the outbound data-strobe

information stream. During transmission, the encoded

data information is transmitted differentially on the TPA

and TPB cable pair(s).

During packet reception, the TPA and TPB

transmitters of the receiving cable port are disabled,

and the receivers for that port are enabled. The

encoded data information is received on the TPA and

TPB cable pair. The received data-strobe information

is decoded to recover the receive clock signal and the

serial data bits. The serial data bits are split into two,

four, or eight parallel streams, resynchronized to the

local system clock, and sent to the associated LLC.

The received data is also transmitted (repeated) out of

the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate

differential comparators to monitor the line states

during initialization and arbitration. The outputs of

these comparators are used by the internal logic to

determine the arbitration status. The TPA channel

monitors the incoming cable common-mode voltage.

The value of this common-mode voltage is used during

arbitration to set the speed of the next packet

transmission. In addition, the TPB channel monitors

the incoming cable common-mode voltage for the

presence of the remotely supplied twisted-pair bias

voltage. This monitor is called bias-detect.

The TPBIAS circuit monitors the value of incoming

TPA pair common-mode voltage when local TPBIAS is

inactive. Because this circuit has an internal current

source and the connected node has a current sink, the

monitored value indicates the cable connection status.

This monitor is called connect-detect.

Both the TPB bias-detect monitor and TPBIAS

connect-detect monitor are used in suspend/resume

signaling and cable connection detection.

The PHY provides a 1.86 V nominal bias voltage for

driver load termination. This bias voltage, when seen

through a cable by a remote receiver, indicates the

presence of an active connection. The value of this

bias voltage has been chosen to allow interoperability

between transceiver chips operating from 5 V or 3 V

nominal supplies. This bias voltage source should be

stabilized by using an external filter capacitor of

approximately 0.33 µF.

The transmitter circuitry, the receiver circuitry, and the

twisted-pair bias voltage circuity are all disabled with a

powerdown condition. The powerdown condition

occurs when the PD input is high. The port transmitter

circuitry, the receiver circuitry, and the TPBIAS output

are also disabled when the port is disabled,

suspended, or disconnected.

The line drivers in the PHY operate in a high-

impedance current mode and are designed to work

with external 112 Ω line-termination resistor networks.

One network is provided at each end of each twisted-

pair cable. Each network is composed of a pair of

series-connected 56 Ω resistors. The midpoint of the

pair of resistors that is directly connected to the

twisted-pair A (TPA) signals is connected to the

Agere Systems Inc.

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