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MC74F256 Просмотр технического описания (PDF) - Motorola => Freescale

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производитель
MC74F256
Motorola
Motorola => Freescale Motorola
MC74F256 Datasheet PDF : 4 Pages
1 2 3 4
DUAL 4-BIT
ADDRESSABLE LATCH
The MC54/74F256 dual addressable latch has four distinct modes of opera-
tion which are selectable by controlling the Clear and Enable inputs (see
Function Table). In the addressable latch mode, data at the Data (D) inputs
is written into the addressed latches. The addressed latches will follow the
Data input with all unaddressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous states and are un-
affected by the Data or Address inputs. To eliminate the possibility of entering
erroneous data in the latches, the enable should be held HIGH (inactive) while
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs
with all other outputs LOW. In the clear mode, all outputs are LOW and unef-
fected by the Address and Data inputs.
Combines Dual Demultiplexer and 8-Bit Latch
Serial-to-Parallel Capability
Output from Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Common Clear Input
Useful as Dual 1-of-4 Active HIGH Decoder
CONNECTION DIAGRAM
VCC MR E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
MC54/74F256
DUAL 4-BIT
ADDRESSABLE LATCH
FASTSCHOTTKY TTL
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
1 2 3 4 56 78
A0 A1 Da Q0a Q1a Q2a Q3a GND
FUNCTION TABLE
Inputs
Outputs
Operating Mode
Master Reset
MR E D A0 A1 Q0 Q1 Q2 Q3
LHXX X
L
L
L
L
Demultiplex (Active
HIGH Decoder when
D = H)
L LdL
L L dH
L LdL
L L dH
L Q=d L
L
L
L
L Q=d L
L
HL
L Q=d L
HL
L
L Q=d
Store (Do Nothing)
H H X X X q0 q1 q2 q3
Addressable
Latch
HLdL
HL dH
HLdL
HL dH
L Q = d q1 q2 q3
L q0 Q = d q2 q3
H q0 q1 Q = d q3
H q0 q1 q2 Q = d
H = HIGH Voltage Level Steady State
L = LOW Voltage Level Steady State
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition.
q = Lower case letters indicate the state of the referenced output established during the last cycle
in which it was addressed or cleared.
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3
13
1 A0
Da
Db
E 14
2 A1
MR 15
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
4 5 6 7 9 10 11 12
FAST AND LS TTL DATA
4-123

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