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FW801BF

Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet

January 2005

FW801BF PHY 1394a-2000

One-Cable Transceiver/Arbiter Device

Signal Information (continued)

Table 2. Signal Descriptions (continued)

Ball

Number

Signal*

Type

Name/Description

H6

SM

I

Test Mode Control. SM is used during Agere’s manufacturing test and

should be tied to VSS for normal operation.

A3

SYSCLK

O

System Clock. SYSCLK provides a 49.152 MHz clock signal, which is

synchronized with the data transfers to the LLC.

F8

TPA[0] Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twisted-

G8

TPAN[0]

pair cable. Board traces from each pair of positive and negative differen-

tial signal balls should be kept as short as possible and matched to the

external load resistors and to the cable connector.

H7

TPB[0] Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twisted-

H8

TPBN[0]

pair cable. Board traces from each pair of positive and negative differen-

tial signal balls should be kept as short as possible and matched to the

external load resistors and to the cable connector.

D7

TPBIAS[0] Analog I/O Port0, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias

voltage needed for proper operation of the twisted-pair cable drivers and

receivers and for sending a valid cable connection signal to the remote

nodes.

B5, D2,

VDD

H2

—

Digital Power. VDD supplies power to the digital portion of the device.

C7, G7

VDDA

—

Analog Circuit Power. VDDA supplies power to the analog portion of the

device.

A6, G3,

VSS

G5, G6

—

Digital Ground. All VSS signals should be tied to the low-impedance

ground plane.

B7, F7

VSSA

—

Analog Circuit Ground. All VSSA signals should be tied together to a low-

impedance ground plane.

A5

XI

A4

XO

—

Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant

fundamental mode crystal. Although, when a 24.576 MHz clock source is

used, it can be connected to XI with XO left unconnected. The optimum

values for the external load capacitors and resistor are dependent on the

specifications of the crystal used. It is necessary to add an external series

resistor (RL) to the XO ball (see Figures 3 and 5). For more details, refer

to the Crystal Selection Considerations section in this data sheet. Note

that it is very important to place the crystal as close as possible to the XO

and XI balls, i.e., within 0.5 in./1.27 cm.

* Active-low signals are indicated by “N” at the end of signal names, within this document.

Agere Systems Inc.

9

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