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FW801BF

Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

FW801BF PHY 1394a-2000

One-Cable Transceiver/Arbiter Device

Data Sheet

January 2005

Description (continued)

The FW801BF supports suspend/resume as defined in

the IEEE 1394a-2000 specification. The suspend

mechanism allows the FW801BF port to be put into a

suspended state. In this state, the port is unable to

transmit or receive data packets; however, it remains

capable of detecting connection status changes and

detecting incoming TPBias. When the FW801BF port

is suspended, all circuits except the bias voltage refer-

ence generator and the bias detection circuits are

powered down, resulting in significant power savings.

The use of suspend/resume is recommended.

As an input, the C_LKON signal indicates whether a

node is a contender for bus manager. When the

C_LKON signal is asserted, it means the node is a

contender for bus manager. When the signal is not

asserted, it means that the node is not a contender.

The C bit corresponds to bit 20 in the self-ID packet

(see Section 4.3.4.1 of the IEEE 1394a-2000 standard

for additional details).

The power class (Pwr_class) bits of the self-ID packet

have a default value of 4, i.e., power class 100. These

bits can be read and modified through the LLC using

Figure 5B-1 (PHY Register Map) of the IEEE 1394a-

2000 standard. See Table 9 of this document for the

address space of the Pwr_class register.

A powerdown signal (PD) is provided to allow a power-

down mode where most of the PHY circuits are

powered down to conserve energy in battery-powered

applications. The internal logic in FW801BF is reset as

long as the powerdown signal is asserted. A cable sta-

tus signal (CNA) provides a high output when the

twisted-pair cable port is receiving incoming bias volt-

age. This output is not debounced. The CNA output

can be used to determine when to power the PHY

down or up. In the powerdown mode, all circuitry is

disabled except the CNA circuitry. It should be noted

that when the device is powered down, it does not act

in a repeater mode.

When the power supply of the PHY is removed while

the twisted-pair cables are connected, the PHY trans-

mitter and receiver circuitry is designed to present a

high impedance to the cable in order to not load the

TPBIAS signal voltage on the other end of the cable.

Whenever the TBA±/TPB± signals are wired to a con-

nector, they must be terminated using the normal

termination network (See Figure 4.). This is required

for reliable operation. When the port does not have a

cable connected, internal connect-detect circuitry will

keep the port in a disconnected state.

All gap counts on all nodes of a 1394 bus must be

identical. The software accomplishes this by issuing

PHY configuration packets (see Section 4.3.4.3 of the

IEEE 1394a-2000 standard) or by issuing two bus

resets, which resets the gap counts to the maximum

level (3Fh).

The link power status (LPS) signal works with the

C_LKON signal to manage the LLC power usage of

the node. The LPS signal indicates that the LLC of the

node is powered up or powered down. If LPS is inac-

tive for more than 1.2 µs and less than 25 µs, the

PHY/link interface is reset. If LPS is inactive for greater

than 25 µs, the PHY will disable the PHY/link interface

to save power. FW801BF continues its repeater func-

tion even when the PHY/link interface is disabled. If

the PHY then receives a link-on packet, the C_LKON

signal is activated to output a 6.114 MHz signal that

can be used by the LLC to power itself up. Once the

LLC is powered up, the LPS signal communicates this

to the PHY and the PHY/link interface is enabled.

C_LKON signal is turned off when LPS is active or

when a bus reset occurs, provided the interrupt that

caused C_LKON is not present.

When the PHY/link interface is in the disabled state,

the FW801BF will automatically enter a low-power

mode if all ports are inactive (disconnected, disabled,

or suspended). In this low-power mode, the FW801BF

disables its PLL and also disables parts of its refer-

ence circuitry depending on the state of the port (some

reference circuitry must remain active in order to

detect incoming TP bias). The lowest power consump-

tion (the microlow-power sleep mode) is attained when

the port is either disconnected or disabled with the port

interrupt enable bit (See Table 12) cleared. The

FW801BF will exit the low-power mode when the LPS

input is asserted high or when a port event occurs that

requires the FW801BF to become active in order to

respond to the event or to notify the LLC of the event

(e.g., incoming bias or disconnection is detected on a

suspended port, a new connection is detected on a

nondisabled port, etc.). When the FW801BF is in the

low-power mode, the SYSCLK output will become

active (and the PHY/link interface will be initialized and

become operative) within 3 ms after LPS is asserted

high.

Two of the FW801BF’s signals are used to set up vari-

ous test conditions used only during the device

manufacturing process. These signals (SE and SM)

should be connected to VSS for normal operation.

4

Agere Systems Inc.

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