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FW801BF

Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device

Agere -> LSI Corporation 

Data Sheet

January 2005

FW801BF PHY 1394a-2000

One-Cable Transceiver/Arbiter Device

Description (continued)

The PHY requires either an external 24.576 MHz crys-

tal or crystal oscillator. The internal oscillator drives an

internal phase-locked loop (PLL) that generates the

required 393.216 MHz reference signal. The 393.216

MHz reference signal is internally divided to provide

the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock

signals that control transmission of the outbound

encoded strobe and data information. The 49.152 MHz

clock signal is also supplied to the associated LLC for

synchronization of the two chips and is used for resyn-

chronization of the received data. The powerdown

function, when enabled by the PD signal high, stops

operation of the PLL and disables all circuitry except

the cable-not-active (CNA) signal circuitry.

The PHY supports an isolation barrier between itself

and its LLC. When ISON is tied high, the link interface

outputs behave normally. When ISON is tied low, inter-

nal differentiating logic is enabled, and the outputs

become short pulses that can be coupled through a

capacitor or transformer as described in the

IEEE 1394-1995 Annex J. To operate with bus-keeper

isolation, the ISON ball of the FW801BF must be tied

high.

Data bits to be transmitted through the cable port is

received from the LLC on two, four, or eight data lines

(D[0:7]), and are latched internally in the PHY in syn-

chronization with the 49.152 MHz system clock. These

bits are combined serially, encoded, and transmitted at

98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as

the outbound data-strobe information stream. During

transmission, the encoded data information is transmit-

ted differentially on the TPA and TPB cable pair(s).

During packet reception, the TPA and TPB transmit-

ters of the receiving cable port are disabled and the

receivers for that port are enabled. The encoded data

information is received on the TPA and TPB cable

pair. The received data-strobe information is decoded

to recover the receive clock signal and the serial data

bits. The serial data bits are split into two (for S100),

four (for S200), or eight (for S400) parallel streams,

resynchronized to the local system clock, and sent to

the associated LLC. The received data is also trans-

mitted (repeated) out of the other active (connected)

cable ports.

Both the TPA and TPB cable interfaces incorporate

differential comparators to monitor the line states dur-

ing initialization and arbitration. The outputs of these

comparators are used by the internal logic to deter-

mine the arbitration status. The TPA channel monitors

the incoming cable common-mode voltage. The value

of this common-mode voltage is used during arbitra-

Agere Systems Inc.

tion to set the speed of the next packet transmission.

In addition, the TPB channel monitors the incoming

cable common-mode voltage for the presence of the

remotely supplied twisted-pair bias voltage. This moni-

tor is called bias-detect.

The TPBIAS circuit monitors the value of incoming

TPA pair common-mode voltage when local TPBIAS is

inactive. Because this circuit has an internal current

source and the connected node has a current sink, the

monitored value indicates the cable connection status.

This monitor is called connect-detect.

Both the TPB bias-detect monitor and TPBIAS con-

nect-detect monitor are used in suspend/resume

signaling and cable connection detection.

The PHY provides a 1.86 V nominal bias voltage for

driver load termination. When seen through a cable by

a remote receiver, this bias voltage indicates the pres-

ence of an active connection. The value of this bias

voltage has been chosen to allow interoperability

between transceiver chips operating from 5 V or 3 V

nominal supplies. This bias voltage source should be

stabilized by using an external filter capacitor of

approximately 0.33 µF.

The transmitter circuitry, the receiver circuitry, and the

twisted-pair bias voltage circuity are all disabled with a

powerdown condition. The powerdown condition

occurs when the PD input is high. The port transmitter

circuitry, the receiver circuitry, and the TPBIAS output

are also disabled when the port is disabled, sus-

pended, or disconnected.

The line drivers in the PHY operate in a high-imped-

ance current mode and are designed to work with

external 112 Ω line-termination resistor networks. One

network is provided at each end of each twisted-pair

cable. Each network is composed of a pair of series-

connected 56 Ω resistors. The midpoint of the pair of

resistors that is directly connected to the twisted-pair A

(TPA) signals is connected to the TPBIAS voltage sig-

nal. The midpoint of the pair of resistors that is directly

connected to the twisted-pair B (TPB) signals is cou-

pled to ground through a parallel RC network with

recommended resistor and capacitor values of 5 kΩ

and 220 pF, respectively. The value of the external

resistors are specified to meet the IEEE 1394 standard

specifications when connected in parallel with the

internal receiver circuits.

The driver output current, along with other internal

operating currents, is set by an external resistor. This

resistor is connected between the R0 and R1 signals

and has a value of 2.49 kΩ ± 1%.

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